[people/ms/u-boot.git] / include / configs / XPEDITE1K.h

/*
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * config for XPedite1000 from XES Inc.
 * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
 * (C) Copyright 2003 Sandburst Corporation
 * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_XPEDITE1K	1		/* Board is XPedite 1000 */
#define CONFIG_4xx		1		/* ... PPC4xx family	*/
#define CONFIG_440		1
#define CONFIG_440GX		1		/* 440 GX */
#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_pre_init	*/
#undef	CONFIG_SYS_DRAM_TEST				/* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll */


/* POST support */
#define CONFIG_POST		(CONFIG_SYS_POST_RTC	   | \
				 CONFIG_SYS_POST_I2C)

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_SDRAM_BASE	    0x00000000		/* _must_ be 0		*/
#define CONFIG_SYS_FLASH_BASE	    0xfff80000		/* start of FLASH	*/

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_FLASH_BASE	/* start of monitor	*/
#define CONFIG_SYS_PCI_MEMBASE	    0x80000000		/* mapped pci memory	*/
#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000		/* internal peripherals */
#define CONFIG_SYS_ISRAM_BASE	    0xc0000000		/* internal SRAM	*/
#define CONFIG_SYS_PCI_BASE	    0xd0000000		/* internal PCI regs	*/

#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
#define CONFIG_SYS_GPIO_BASE	    (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)

#define USR_LED0	    0x00000080
#define USR_LED1	    0x00000100
#define USR_LED2	    0x00000200
#define USR_LED3	    0x00000400

#ifndef __ASSEMBLY__
extern unsigned long in32(unsigned int);
extern void out32(unsigned int, unsigned long);

#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0))
#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1))
#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2))
#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3))

#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0))
#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1))
#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2))
#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
#endif

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_TEMP_STACK_OCM  1
#define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
#define CONFIG_SYS_GBL_DATA_SIZE   128		    /* num bytes initial data	*/


#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_POST_WORD_ADDR  (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_POST_WORD_ADDR

#define CONFIG_SYS_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
#define CONFIG_SYS_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_BAUDRATE		9600

#define CONFIG_SYS_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}

/*-----------------------------------------------------------------------
 * NVRAM/RTC
 *
 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
 * The DS1743 code assumes this condition (i.e. -- it assumes the base
 * address for the RTC registers is:
 *
 *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
 *
 *----------------------------------------------------------------------*/
/* TBS:	 Xpedite 1000 has STMicro M41T00 via IIC */
#define CONFIG_RTC_M41T11 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_M41T11_BASE_YEAR 2000

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_FLASH_BANKS	1		    /* number of banks	    */
#define CONFIG_SYS_MAX_FLASH_SECT	8		    /* sectors per device   */

#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	    /* Timeout for Flash Write (in ms)	*/

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
#define SPD_EEPROM_ADDRESS {0x54}	/* SPD i2c spd addresses	*/
#define CONFIG_VERY_BIG_RAM 1
/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7f
#define CONFIG_SYS_I2C_NOPROBES	{0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69}	/* Don't probe these addrs */

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#define CONFIG_ENV_IS_IN_EEPROM 1
#define CONFIG_ENV_SIZE		0x100	    /* Size of Environment vars */
#define CONFIG_ENV_OFFSET		0x100
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* this is actually the second page of the eeprom */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10

#define CONFIG_BOOTARGS		"root=/dev/hda1 "
#define CONFIG_BOOTCOMMAND	"bootm ffc00000"    /* autoboot command */
#define CONFIG_BOOTDELAY	5		    /* disable autoboot */
#define CONFIG_BAUDRATE		9600

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII			1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address phy0 not populated */
#define CONFIG_PHY1_ADDR	1	/* PHY address phy1 not populated */
#define CONFIG_PHY2_ADDR	4	/* PHY address phy2 */
#define CONFIG_PHY3_ADDR	8	/* PHY address phy3 */
#define CONFIG_NET_MULTI	1
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
#define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
#define CONFIG_SYS_RX_ETH_BUFFER   32	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
#define CONFIG_HAS_ETH2		1	/* add support for "eth2addr"	*/
#define CONFIG_HAS_ETH3		1	/* add support for "eth3addr"	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DATE
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MII
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_FAT


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */


/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI				    /* include pci support		*/
#define CONFIG_PCI_PNP				/* do pci plug-and-play		*/
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
#define CONFIG_SYS_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT		    /* let board init pci target    */

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
#define CONFIG_SYS_PCI_FORCE_PCI_CONV          /* Force PCI Conventional Mode */
/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
ba56f625 WD	1	/*
	2	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	/************************************************************************
	24	* config for XPedite1000 from XES Inc.
	25	* Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
	26	* (C) Copyright 2003 Sandburst Corporation
0c8721a4	27	* board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
ba56f625 WD	28	***********************************************************************/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32
	33	/*-----------------------------------------------------------------------
	34	* High Level Configuration Options
	35	----------------------------------------------------------------------/
	36	#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */
	37	#define CONFIG_4xx 1 /* ... PPC4xx family */
	38	#define CONFIG_440 1
846b0dd2	39	#define CONFIG_440GX 1 /* 440 GX */
3c74e32a	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
6d0f6bcf	41	#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time! */
ba56f625 WD	42	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
	43
	44
	45	/* POST support */
6d0f6bcf JCPV	46	#define CONFIG_POST (CONFIG_SYS_POST_RTC \| \
6d0f6bcf JCPV	47	CONFIG_SYS_POST_I2C)
ba56f625 WD	48
	49	/*-----------------------------------------------------------------------
	50	* Base addresses -- Note these are effective addresses where the
	51	* actual resources get mapped (not physical addresses)
	52	----------------------------------------------------------------------/
6d0f6bcf JCPV	53	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
6d0f6bcf JCPV	54	#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
ba56f625	55
6d0f6bcf JCPV	56	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* start of monitor */
	57	#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
	58	#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
	59	#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
	60	#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
ba56f625	61
6d0f6bcf JCPV	62	#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
6d0f6bcf JCPV	63	#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
ba56f625 WD	64
	65	#define USR_LED0 0x00000080
	66	#define USR_LED1 0x00000100
	67	#define USR_LED2 0x00000200
	68	#define USR_LED3 0x00000400
	69
	70	#ifndef __ASSEMBLY__
	71	extern unsigned long in32(unsigned int);
	72	extern void out32(unsigned int, unsigned long);
	73
6d0f6bcf JCPV	74	#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0))
	75	#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1))
	76	#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2))
	77	#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3))
ba56f625	78
6d0f6bcf JCPV	79	#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) \| USR_LED0))
	80	#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) \| USR_LED1))
	81	#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) \| USR_LED2))
	82	#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) \| USR_LED3))
ba56f625 WD	83	#endif
	84
	85	/*-----------------------------------------------------------------------
	86	* Initial RAM & stack pointer (placed in internal SRAM)
	87	----------------------------------------------------------------------/
6d0f6bcf JCPV	88	#define CONFIG_SYS_TEMP_STACK_OCM 1
	89	#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
	90	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
	91	#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
	92	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
ba56f625 WD	93
ba56f625 WD	94
6d0f6bcf JCPV	95	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	96	#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
	97	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
ba56f625	98
6d0f6bcf JCPV	99	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	100	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
ba56f625 WD	101
	102	/*-----------------------------------------------------------------------
	103	* Serial Port
	104	----------------------------------------------------------------------/
	105	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	106	#define CONFIG_BAUDRATE 9600
	107
6d0f6bcf	108	#define CONFIG_SYS_BAUDRATE_TABLE \
ba56f625 WD	109	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
	110
	111	/*-----------------------------------------------------------------------
	112	* NVRAM/RTC
	113	*
	114	* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
	115	* The DS1743 code assumes this condition (i.e. -- it assumes the base
	116	* address for the RTC registers is:
	117	*
6d0f6bcf	118	* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
ba56f625 WD	119	*
	120	----------------------------------------------------------------------/
	121	/* TBS: Xpedite 1000 has STMicro M41T00 via IIC */
	122	#define CONFIG_RTC_M41T11 1
6d0f6bcf JCPV	123	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
6d0f6bcf JCPV	124	#define CONFIG_SYS_M41T11_BASE_YEAR 2000
ba56f625 WD	125
	126	/*-----------------------------------------------------------------------
	127	* FLASH related
	128	----------------------------------------------------------------------/
6d0f6bcf JCPV	129	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
6d0f6bcf JCPV	130	#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
ba56f625	131
6d0f6bcf JCPV	132	#undef CONFIG_SYS_FLASH_CHECKSUM
	133	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	134	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
ba56f625 WD	135
	136	/*-----------------------------------------------------------------------
	137	* DDR SDRAM
	138	----------------------------------------------------------------------/
	139	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
	140	#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */
	141	#define CONFIG_VERY_BIG_RAM 1
	142	/*-----------------------------------------------------------------------
	143	* I2C
	144	----------------------------------------------------------------------/
	145	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	146	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	147	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
	148	#define CONFIG_SYS_I2C_SLAVE 0x7f
	149	#define CONFIG_SYS_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} /* Don't probe these addrs */
ba56f625 WD	150
	151	/*-----------------------------------------------------------------------
	152	* Environment
	153	----------------------------------------------------------------------/
bb1f8b4f	154	#define CONFIG_ENV_IS_IN_EEPROM 1
0e8d1586 JCPV	155	#define CONFIG_ENV_SIZE 0x100 /* Size of Environment vars */
0e8d1586 JCPV	156	#define CONFIG_ENV_OFFSET 0x100
6d0f6bcf JCPV	157	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* this is actually the second page of the eeprom */
	158	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	159	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	160	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
ba56f625 WD	161
	162	#define CONFIG_BOOTARGS "root=/dev/hda1 "
	163	#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
e7c85689	164	#define CONFIG_BOOTDELAY 5 /* disable autoboot */
ba56f625 WD	165	#define CONFIG_BAUDRATE 9600
	166
	167	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	168	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
ba56f625 WD	169
	170	#define CONFIG_MII 1 /* MII PHY management */
	171	#define CONFIG_PHY_ADDR 0 /* PHY address phy0 not populated */
	172	#define CONFIG_PHY1_ADDR 1 /* PHY address phy1 not populated */
	173	#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */
	174	#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */
	175	#define CONFIG_NET_MULTI 1
6fb6af6d	176	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
d6c61aab	177	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
6d0f6bcf	178	#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
ba56f625	179
e2ffd59b WD	180	#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
	181	#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
	182	#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
	183
a5562901	184
a1aa0bb5 JL	185	/*
	186	* BOOTP options
	187	*/
	188	#define CONFIG_BOOTP_BOOTFILESIZE
	189	#define CONFIG_BOOTP_BOOTPATH
	190	#define CONFIG_BOOTP_GATEWAY
	191	#define CONFIG_BOOTP_HOSTNAME
	192
	193
a5562901 JL	194	/*
	195	* Command line configuration.
	196	*/
	197	#include <config_cmd_default.h>
	198
	199	#define CONFIG_CMD_PCI
	200	#define CONFIG_CMD_IRQ
	201	#define CONFIG_CMD_I2C
	202	#define CONFIG_CMD_DATE
	203	#define CONFIG_CMD_BEDBUG
	204	#define CONFIG_CMD_EEPROM
	205	#define CONFIG_CMD_PING
	206	#define CONFIG_CMD_ELF
	207	#define CONFIG_CMD_MII
	208	#define CONFIG_CMD_DIAG
	209	#define CONFIG_CMD_FAT
	210
ba56f625 WD	211
	212	#undef CONFIG_WATCHDOG /* watchdog disabled */
	213
	214	/*
	215	* Miscellaneous configurable options
	216	*/
6d0f6bcf JCPV	217	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	218	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
a5562901	219	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	220	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
ba56f625	221	#else
6d0f6bcf	222	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
ba56f625	223	#endif
6d0f6bcf JCPV	224	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	225	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	226	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
ba56f625	227
6d0f6bcf JCPV	228	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	229	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
ba56f625	230
6d0f6bcf JCPV	231	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	232	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
ba56f625	233
6d0f6bcf	234	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
ba56f625 WD	235
	236
	237	/*-----------------------------------------------------------------------
	238	* PCI stuff
	239	*-----------------------------------------------------------------------
	240	*/
	241	/* General PCI */
	242	#define CONFIG_PCI /* include pci support */
	243	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	244	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	245	#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
ba56f625 WD	246
ba56f625 WD	247	/* Board-specific PCI */
6d0f6bcf	248	#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
ba56f625	249
6d0f6bcf JCPV	250	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
	251	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
	252	#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */
ba56f625 WD	253	/*
	254	* For booting Linux, the board info and command line data
	255	* have to be in the first 8 MB of memory, since this is
	256	* the maximum mapped by the Linux kernel during initialization.
	257	*/
6d0f6bcf	258	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
ba56f625 WD	259
	260	/*
	261	* Internal Definitions
	262	*
	263	* Boot Flags
	264	*/
	265	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	266	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	267
a5562901	268	#if defined(CONFIG_CMD_KGDB)
ba56f625 WD	269	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	270	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	271	#endif
	272	#endif /* __CONFIG_H */