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ba56f625 WD |
1 | /* |
2 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /************************************************************************ | |
24 | * config for XPedite1000 from XES Inc. | |
25 | * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com> | |
26 | * (C) Copyright 2003 Sandburst Corporation | |
0c8721a4 | 27 | * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony) |
ba56f625 WD |
28 | ***********************************************************************/ |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
33 | /*----------------------------------------------------------------------- | |
34 | * High Level Configuration Options | |
35 | *----------------------------------------------------------------------*/ | |
36 | #define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */ | |
37 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
38 | #define CONFIG_440 1 | |
846b0dd2 | 39 | #define CONFIG_440GX 1 /* 440 GX */ |
3c74e32a | 40 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
ba56f625 WD |
41 | #undef CFG_DRAM_TEST /* Disable-takes long time! */ |
42 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ | |
43 | ||
44 | ||
45 | /* POST support */ | |
46 | #define CONFIG_POST (CFG_POST_RTC | \ | |
47 | CFG_POST_I2C) | |
48 | ||
49 | /*----------------------------------------------------------------------- | |
50 | * Base addresses -- Note these are effective addresses where the | |
51 | * actual resources get mapped (not physical addresses) | |
52 | *----------------------------------------------------------------------*/ | |
53 | #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
54 | #define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ | |
55 | ||
56 | #define CFG_MONITOR_BASE CFG_FLASH_BASE /* start of monitor */ | |
57 | #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
58 | #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ | |
59 | #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ | |
60 | #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
61 | ||
62 | #define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) | |
63 | #define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) | |
64 | ||
65 | #define USR_LED0 0x00000080 | |
66 | #define USR_LED1 0x00000100 | |
67 | #define USR_LED2 0x00000200 | |
68 | #define USR_LED3 0x00000400 | |
69 | ||
70 | #ifndef __ASSEMBLY__ | |
71 | extern unsigned long in32(unsigned int); | |
72 | extern void out32(unsigned int, unsigned long); | |
73 | ||
74 | #define LED0_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED0)) | |
75 | #define LED1_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED1)) | |
76 | #define LED2_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED2)) | |
77 | #define LED3_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED3)) | |
78 | ||
79 | #define LED0_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED0)) | |
80 | #define LED1_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED1)) | |
81 | #define LED2_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED2)) | |
82 | #define LED3_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED3)) | |
83 | #endif | |
84 | ||
85 | /*----------------------------------------------------------------------- | |
86 | * Initial RAM & stack pointer (placed in internal SRAM) | |
87 | *----------------------------------------------------------------------*/ | |
e7c85689 WD |
88 | #define CFG_TEMP_STACK_OCM 1 |
89 | #define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE | |
ba56f625 WD |
90 | #define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ |
91 | #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ | |
92 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
93 | ||
94 | ||
95 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
96 | #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) | |
97 | #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR | |
98 | ||
99 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
100 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ | |
101 | ||
102 | /*----------------------------------------------------------------------- | |
103 | * Serial Port | |
104 | *----------------------------------------------------------------------*/ | |
105 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
106 | #define CONFIG_BAUDRATE 9600 | |
107 | ||
108 | #define CFG_BAUDRATE_TABLE \ | |
109 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} | |
110 | ||
111 | /*----------------------------------------------------------------------- | |
112 | * NVRAM/RTC | |
113 | * | |
114 | * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. | |
115 | * The DS1743 code assumes this condition (i.e. -- it assumes the base | |
116 | * address for the RTC registers is: | |
117 | * | |
118 | * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE | |
119 | * | |
120 | *----------------------------------------------------------------------*/ | |
121 | /* TBS: Xpedite 1000 has STMicro M41T00 via IIC */ | |
122 | #define CONFIG_RTC_M41T11 1 | |
123 | #define CFG_I2C_RTC_ADDR 0x68 | |
124 | #define CFG_M41T11_BASE_YEAR 2000 | |
125 | ||
126 | /*----------------------------------------------------------------------- | |
127 | * FLASH related | |
128 | *----------------------------------------------------------------------*/ | |
129 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
130 | #define CFG_MAX_FLASH_SECT 8 /* sectors per device */ | |
131 | ||
132 | #undef CFG_FLASH_CHECKSUM | |
133 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
134 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
135 | ||
136 | /*----------------------------------------------------------------------- | |
137 | * DDR SDRAM | |
138 | *----------------------------------------------------------------------*/ | |
139 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ | |
140 | #define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */ | |
141 | #define CONFIG_VERY_BIG_RAM 1 | |
142 | /*----------------------------------------------------------------------- | |
143 | * I2C | |
144 | *----------------------------------------------------------------------*/ | |
145 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
146 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
147 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
148 | #define CFG_I2C_SLAVE 0x7f | |
149 | #define CFG_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} /* Don't probe these addrs */ | |
150 | ||
151 | /*----------------------------------------------------------------------- | |
152 | * Environment | |
153 | *----------------------------------------------------------------------*/ | |
bb1f8b4f | 154 | #define CONFIG_ENV_IS_IN_EEPROM 1 |
ba56f625 WD |
155 | #define CFG_ENV_SIZE 0x100 /* Size of Environment vars */ |
156 | #define CFG_ENV_OFFSET 0x100 | |
157 | #define CFG_I2C_EEPROM_ADDR 0x50 /* this is actually the second page of the eeprom */ | |
158 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
159 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
160 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 | |
161 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
162 | ||
163 | #define CONFIG_BOOTARGS "root=/dev/hda1 " | |
164 | #define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ | |
e7c85689 | 165 | #define CONFIG_BOOTDELAY 5 /* disable autoboot */ |
ba56f625 WD |
166 | #define CONFIG_BAUDRATE 9600 |
167 | ||
168 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
169 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
170 | ||
171 | #define CONFIG_MII 1 /* MII PHY management */ | |
172 | #define CONFIG_PHY_ADDR 0 /* PHY address phy0 not populated */ | |
173 | #define CONFIG_PHY1_ADDR 1 /* PHY address phy1 not populated */ | |
174 | #define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */ | |
175 | #define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */ | |
176 | #define CONFIG_NET_MULTI 1 | |
6fb6af6d | 177 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
d6c61aab | 178 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
ba56f625 WD |
179 | #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
180 | ||
e2ffd59b WD |
181 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
182 | #define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */ | |
183 | #define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ | |
184 | ||
a5562901 | 185 | |
a1aa0bb5 JL |
186 | /* |
187 | * BOOTP options | |
188 | */ | |
189 | #define CONFIG_BOOTP_BOOTFILESIZE | |
190 | #define CONFIG_BOOTP_BOOTPATH | |
191 | #define CONFIG_BOOTP_GATEWAY | |
192 | #define CONFIG_BOOTP_HOSTNAME | |
193 | ||
194 | ||
a5562901 JL |
195 | /* |
196 | * Command line configuration. | |
197 | */ | |
198 | #include <config_cmd_default.h> | |
199 | ||
200 | #define CONFIG_CMD_PCI | |
201 | #define CONFIG_CMD_IRQ | |
202 | #define CONFIG_CMD_I2C | |
203 | #define CONFIG_CMD_DATE | |
204 | #define CONFIG_CMD_BEDBUG | |
205 | #define CONFIG_CMD_EEPROM | |
206 | #define CONFIG_CMD_PING | |
207 | #define CONFIG_CMD_ELF | |
208 | #define CONFIG_CMD_MII | |
209 | #define CONFIG_CMD_DIAG | |
210 | #define CONFIG_CMD_FAT | |
211 | ||
ba56f625 WD |
212 | |
213 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
214 | ||
215 | /* | |
216 | * Miscellaneous configurable options | |
217 | */ | |
218 | #define CFG_LONGHELP /* undef to save memory */ | |
219 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
a5562901 | 220 | #if defined(CONFIG_CMD_KGDB) |
ba56f625 WD |
221 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
222 | #else | |
223 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
224 | #endif | |
225 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
226 | #define CFG_MAXARGS 16 /* max number of command args */ | |
227 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
228 | ||
229 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
230 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
231 | ||
232 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
233 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
234 | ||
235 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
236 | ||
237 | ||
238 | /*----------------------------------------------------------------------- | |
239 | * PCI stuff | |
240 | *----------------------------------------------------------------------- | |
241 | */ | |
242 | /* General PCI */ | |
243 | #define CONFIG_PCI /* include pci support */ | |
244 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
245 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
246 | #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ | |
247 | ||
248 | /* Board-specific PCI */ | |
ba56f625 WD |
249 | #define CFG_PCI_TARGET_INIT /* let board init pci target */ |
250 | ||
251 | #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ | |
252 | #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
3c74e32a | 253 | #define CFG_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */ |
ba56f625 WD |
254 | /* |
255 | * For booting Linux, the board info and command line data | |
256 | * have to be in the first 8 MB of memory, since this is | |
257 | * the maximum mapped by the Linux kernel during initialization. | |
258 | */ | |
259 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
ba56f625 WD |
260 | |
261 | /* | |
262 | * Internal Definitions | |
263 | * | |
264 | * Boot Flags | |
265 | */ | |
266 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
267 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
268 | ||
a5562901 | 269 | #if defined(CONFIG_CMD_KGDB) |
ba56f625 WD |
270 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
271 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
272 | #endif | |
273 | #endif /* __CONFIG_H */ |