[people/ms/u-boot.git] / include / configs / ZPC1900.h

/*
 * Copyright (C) 2003-2005 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 *
 * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
 * This port was developed and tested on Revision C board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU      */
#define CONFIG_ZPC1900		1	/* ...on Zephyr ZPC.1900 board */
#define CPU_ID_STR		"MPC8265"
#define CONFIG_CPM2		1	/* Has a CPM2 */

/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_ENV_OVERWRITE

/*
 * Select serial console configuration
 *
 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 */
#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
#undef	CONFIG_CONS_NONE		/* It's not on external UART */
#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */

/*
 * Select ethernet configuration
 *
 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
 * SCC, 1-3 for FCC)
 *
 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
 * must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */

#ifdef CONFIG_ETHER_ON_FCC

#define CONFIG_ETHER_INDEX	2	/* FCC2 is used for Ethernet */

#if (CONFIG_ETHER_INDEX == 2)
/*
 * - Rx clock is CLK13
 * - Tx clock is CLK14
 * - Select bus for bd/buffers (see 28-13)
 * - Full duplex
 */
# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
# define CFG_CPMFCR_RAMTYPE	0
# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#endif /* CONFIG_ETHER_INDEX */

#define CONFIG_MII			/* MII PHY management        */
#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT		2	/* Port C */
#define MDIO_ACTIVE		(iop->pdir |=  0x00400000)
#define MDIO_TRISTATE		(iop->pdir &= ~0x00400000)
#define MDIO_READ		((iop->pdat &  0x00400000) != 0)

#define MDIO(bit)		if(bit) iop->pdat |=  0x00400000; \
				else	iop->pdat &= ~0x00400000

#define MDC(bit)		if(bit) iop->pdat |=  0x00200000; \
				else	iop->pdat &= ~0x00200000

#define MIIDELAY		udelay(1)

#endif /* CONFIG_ETHER_ON_FCC */

#ifndef CONFIG_8260_CLKIN
#define CONFIG_8260_CLKIN	66666666	/* in Hz */
#endif

#define CONFIG_BAUDRATE		38400


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING


#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND	"dhcp;bootm"	/* autoboot command */
#define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=:::::eth0:dhcp"

#if defined(CONFIG_CMD_KGDB)
#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
#endif

#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */

/*
 * Miscellaneous configurable options
 */
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2	"> "
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
#define CFG_MAXARGS		16		/* max number of command args */
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x03800000	/* 1 ... 56 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x400000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CFG_SDRAM_BASE		0x00000000
#define CFG_SDRAM_SIZE		64

#define CFG_IMMR		0xF0000000
#define CFG_LSDRAM_BASE		0xFC000000
#define CFG_FLASH_BASE		0xFE000000
#define CFG_BCSR		0xFEA00000
#define CFG_EEPROM		0xFEB00000
#define CFG_FLSIMM_BASE		0xFF000000

#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
#define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks	*/
#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */

#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLSIMM_BASE }

#define BCSR_PCI_MODE		0x01

#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/* Hard reset configuration word */
#define CFG_HRCW_MASTER		(HRCW_EBM | HRCW_BPS01| HRCW_CIP          |\
				 HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
				 HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10     |\
				 HRCW_MODCK_H0111                          \
				) /* 0x16848207 */
/* No slaves */
#define CFG_HRCW_SLAVE1 	0
#define CFG_HRCW_SLAVE2 	0
#define CFG_HRCW_SLAVE3 	0
#define CFG_HRCW_SLAVE4 	0
#define CFG_HRCW_SLAVE5 	0
#define CFG_HRCW_SLAVE6 	0
#define CFG_HRCW_SLAVE7 	0

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot                  */

#define CFG_MONITOR_BASE	TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#endif

#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#if !defined(CFG_ENV_IS_IN_FLASH) && !defined(CFG_ENV_IS_IN_NVRAM)
#define CFG_ENV_IS_IN_NVRAM	1
#endif

#ifdef CFG_ENV_IS_IN_FLASH
#  define CFG_ENV_SECT_SIZE	0x10000
#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#else
#  define CFG_ENV_ADDR		(CFG_EEPROM + 0x400)
#  define CFG_ENV_SIZE		0x1000
#  define CFG_NVRAM_ACCESS_ROUTINE
#endif

#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

#define CFG_HID0_INIT		(HID0_ICFI)
#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)

#define CFG_HID2		0

#define CFG_SIUMCR		0x42200000
#define CFG_SYPCR		0xFFFFFFC3
#define CFG_BCR			0x90000000
#define CFG_SCCR		SCCR_DFBRG01

#define CFG_RMR			RMR_CSRE
#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
#define CFG_RCCR		0

#define CFG_PSDMR		/* 0x834DA43B */0x014DA43A
#define CFG_PSRT		0x0F/* 0x0C */
#define CFG_LSDMR		0x0085A562
#define CFG_LSRT		0x0F
#define CFG_MPTPR		0x4000

#define CFG_PSDRAM_BR		(CFG_SDRAM_BASE | 0x00000041)
#define CFG_PSDRAM_OR		0xFC0028C0
#define CFG_LSDRAM_BR		(CFG_LSDRAM_BASE | 0x00001861)
#define CFG_LSDRAM_OR		0xFF803480

#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00000801)
#define CFG_OR0_PRELIM		0xFFE00856
#define CFG_BR5_PRELIM		(CFG_EEPROM | 0x00000801)
#define CFG_OR5_PRELIM		0xFFFF03F6
#define CFG_BR6_PRELIM		(CFG_FLSIMM_BASE | 0x00001801)
#define CFG_OR6_PRELIM		0xFF000856
#define CFG_BR7_PRELIM		(CFG_BCSR | 0x00000801)
#define CFG_OR7_PRELIM		0xFFFF83F6

#define CFG_RESET_ADDRESS	0xC0000000

#endif /* __CONFIG_H */
Commit	Line	Data
54387ac9	1	/*
aba9f1af	2	* Copyright (C) 2003-2005 Arabella Software Ltd.
54387ac9 WD	3	* Yuli Barcohen <yuli@arabellasw.com>
	4	*
	5	* U-Boot configuration for Zephyr Engineering ZPC.1900 board.
	6	* This port was developed and tested on Revision C board.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
	31	#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */
	32	#define CPU_ID_STR "MPC8265"
9c4c5ae3	33	#define CONFIG_CPM2 1 /* Has a CPM2 */
54387ac9	34
aba9f1af	35	/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
54387ac9 WD	36	#define CONFIG_ENV_OVERWRITE
	37
	38	/*
	39	* Select serial console configuration
	40	*
	41	* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	42	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	43	* for SCC).
	44	*/
	45	#define CONFIG_CONS_ON_SMC /* Console is on SMC */
	46	#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
	47	#undef CONFIG_CONS_NONE /* It's not on external UART */
	48	#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
	49
	50	/*
	51	* Select ethernet configuration
	52	*
	53	* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
	54	* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
	55	* SCC, 1-3 for FCC)
	56	*
	57	* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
639221c7 JL	58	* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
639221c7 JL	59	* must be unset.
54387ac9 WD	60	*/
	61	#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
	62	#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
	63	#undef CONFIG_ETHER_NONE /* No external Ethernet */
	64
	65	#ifdef CONFIG_ETHER_ON_FCC
	66
	67	#define CONFIG_ETHER_INDEX 2 /* FCC2 is used for Ethernet */
	68
	69	#if (CONFIG_ETHER_INDEX == 2)
	70	/*
	71	* - Rx clock is CLK13
	72	* - Tx clock is CLK14
	73	* - Select bus for bd/buffers (see 28-13)
	74	* - Full duplex
	75	*/
	76	# define CFG_CMXFCR_MASK (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
	77	# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
	78	# define CFG_CPMFCR_RAMTYPE 0
	79	# define CFG_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB)
	80
659883c2	81	#endif /* CONFIG_ETHER_INDEX */
54387ac9 WD	82
	83	#define CONFIG_MII /* MII PHY management */
	84	#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
	85	/*
	86	* GPIO pins used for bit-banged MII communications
	87	*/
659883c2 WD	88	#define MDIO_PORT 2 /* Port C */
	89	#define MDIO_ACTIVE (iop->pdir \|= 0x00400000)
	90	#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
	91	#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
54387ac9	92
659883c2 WD	93	#define MDIO(bit) if(bit) iop->pdat \|= 0x00400000; \
659883c2 WD	94	else iop->pdat &= ~0x00400000
54387ac9	95
659883c2 WD	96	#define MDC(bit) if(bit) iop->pdat \|= 0x00200000; \
659883c2 WD	97	else iop->pdat &= ~0x00200000
54387ac9	98
659883c2	99	#define MIIDELAY udelay(1)
54387ac9 WD	100
	101	#endif /* CONFIG_ETHER_ON_FCC */
	102
	103	#ifndef CONFIG_8260_CLKIN
	104	#define CONFIG_8260_CLKIN 66666666 /* in Hz */
	105	#endif
	106
659883c2 WD	107	#define CONFIG_BAUDRATE 38400
659883c2 WD	108
54387ac9	109
a1aa0bb5 JL	110	/*
	111	* BOOTP options
	112	*/
	113	#define CONFIG_BOOTP_BOOTFILESIZE
	114	#define CONFIG_BOOTP_BOOTPATH
	115	#define CONFIG_BOOTP_GATEWAY
	116	#define CONFIG_BOOTP_HOSTNAME
	117
	118
a5562901 JL	119	/*
	120	* Command line configuration.
	121	*/
	122	#include <config_cmd_default.h>
	123
	124	#define CONFIG_CMD_ASKENV
	125	#define CONFIG_CMD_DHCP
	126	#define CONFIG_CMD_IMMAP
	127	#define CONFIG_CMD_MII
	128	#define CONFIG_CMD_PING
	129
54387ac9 WD	130
	131	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	132	#define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */
	133	#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp"
	134
a5562901	135	#if defined(CONFIG_CMD_KGDB)
54387ac9 WD	136	#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
	137	#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
	138	#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
	139	#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
	140	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
	141	#endif
	142
	143	#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
659883c2	144	#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
54387ac9 WD	145
	146	/*
	147	* Miscellaneous configurable options
	148	*/
	149	#define CFG_HUSH_PARSER
659883c2	150	#define CFG_PROMPT_HUSH_PS2 "> "
54387ac9	151	#define CFG_LONGHELP /* undef to save memory */
659883c2	152	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
a5562901	153	#if defined(CONFIG_CMD_KGDB)
659883c2	154	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
54387ac9	155	#else
659883c2	156	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
54387ac9 WD	157	#endif
	158	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	159	#define CFG_MAXARGS 16 /* max number of command args */
	160	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	161
	162	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
aba9f1af	163	#define CFG_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */
54387ac9	164
aba9f1af	165	#define CFG_LOAD_ADDR 0x400000 /* default load address */
54387ac9 WD	166
	167	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	168
	169	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	170
54387ac9 WD	171	#define CFG_SDRAM_BASE 0x00000000
54387ac9 WD	172	#define CFG_SDRAM_SIZE 64
aba9f1af WD	173
	174	#define CFG_IMMR 0xF0000000
	175	#define CFG_LSDRAM_BASE 0xFC000000
	176	#define CFG_FLASH_BASE 0xFE000000
54387ac9 WD	177	#define CFG_BCSR 0xFEA00000
54387ac9 WD	178	#define CFG_EEPROM 0xFEB00000
aba9f1af	179	#define CFG_FLSIMM_BASE 0xFF000000
54387ac9	180
aba9f1af WD	181	#define CFG_FLASH_CFI
	182	#define CFG_FLASH_CFI_DRIVER
	183	#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
	184	#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
	185
	186	#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLSIMM_BASE }
54387ac9 WD	187
	188	#define BCSR_PCI_MODE 0x01
	189
	190	#define CFG_INIT_RAM_ADDR CFG_IMMR
	191	#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
	192	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	193	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	194	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	195
	196	/* Hard reset configuration word */
659883c2	197	#define CFG_HRCW_MASTER (HRCW_EBM \| HRCW_BPS01\| HRCW_CIP \|\
aba9f1af WD	198	HRCW_L2CPC10 \| HRCW_DPPC00 \| HRCW_ISB100 \|\
	199	HRCW_BMS \| HRCW_LBPC00 \| HRCW_APPC10 \|\
	200	HRCW_MODCK_H0111 \
	201	) /* 0x16848207 */
54387ac9 WD	202	/* No slaves */
	203	#define CFG_HRCW_SLAVE1 0
	204	#define CFG_HRCW_SLAVE2 0
	205	#define CFG_HRCW_SLAVE3 0
	206	#define CFG_HRCW_SLAVE4 0
	207	#define CFG_HRCW_SLAVE5 0
	208	#define CFG_HRCW_SLAVE6 0
	209	#define CFG_HRCW_SLAVE7 0
	210
	211	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	212	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	213
	214	#define CFG_MONITOR_BASE TEXT_BASE
	215	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	216	#define CFG_RAMBOOT
	217	#endif
	218
aba9f1af	219	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
54387ac9 WD	220	#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
	221	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	222
	223	#if !defined(CFG_ENV_IS_IN_FLASH) && !defined(CFG_ENV_IS_IN_NVRAM)
	224	#define CFG_ENV_IS_IN_NVRAM 1
	225	#endif
	226
	227	#ifdef CFG_ENV_IS_IN_FLASH
	228	# define CFG_ENV_SECT_SIZE 0x10000
659883c2	229	# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
54387ac9 WD	230	#else
54387ac9 WD	231	# define CFG_ENV_ADDR (CFG_EEPROM + 0x400)
659883c2	232	# define CFG_ENV_SIZE 0x1000
54387ac9 WD	233	# define CFG_NVRAM_ACCESS_ROUTINE
	234	#endif
	235
	236	#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
a5562901	237	#if defined(CONFIG_CMD_KGDB)
54387ac9 WD	238	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	239	#endif
	240
aba9f1af WD	241	#define CFG_HID0_INIT (HID0_ICFI)
aba9f1af WD	242	#define CFG_HID0_FINAL (HID0_ICE \| HID0_IFEM \| HID0_ABE)
54387ac9 WD	243
	244	#define CFG_HID2 0
	245
	246	#define CFG_SIUMCR 0x42200000
	247	#define CFG_SYPCR 0xFFFFFFC3
aba9f1af	248	#define CFG_BCR 0x90000000
54387ac9 WD	249	#define CFG_SCCR SCCR_DFBRG01
	250
	251	#define CFG_RMR RMR_CSRE
	252	#define CFG_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
	253	#define CFG_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
	254	#define CFG_RCCR 0
	255
aba9f1af WD	256	#define CFG_PSDMR /* 0x834DA43B */0x014DA43A
	257	#define CFG_PSRT 0x0F/* 0x0C */
	258	#define CFG_LSDMR 0x0085A562
	259	#define CFG_LSRT 0x0F
54387ac9 WD	260	#define CFG_MPTPR 0x4000
54387ac9 WD	261
e4dbe1b2	262	#define CFG_PSDRAM_BR (CFG_SDRAM_BASE \| 0x00000041)
aba9f1af	263	#define CFG_PSDRAM_OR 0xFC0028C0
e4dbe1b2	264	#define CFG_LSDRAM_BR (CFG_LSDRAM_BASE \| 0x00001861)
aba9f1af WD	265	#define CFG_LSDRAM_OR 0xFF803480
aba9f1af WD	266
e4dbe1b2	267	#define CFG_BR0_PRELIM (CFG_FLASH_BASE \| 0x00000801)
54387ac9	268	#define CFG_OR0_PRELIM 0xFFE00856
e4dbe1b2	269	#define CFG_BR5_PRELIM (CFG_EEPROM \| 0x00000801)
54387ac9	270	#define CFG_OR5_PRELIM 0xFFFF03F6
e4dbe1b2	271	#define CFG_BR6_PRELIM (CFG_FLSIMM_BASE \| 0x00001801)
aba9f1af	272	#define CFG_OR6_PRELIM 0xFF000856
e4dbe1b2	273	#define CFG_BR7_PRELIM (CFG_BCSR \| 0x00000801)
54387ac9 WD	274	#define CFG_OR7_PRELIM 0xFFFF83F6
	275
	276	#define CFG_RESET_ADDRESS 0xC0000000
	277
	278	#endif /* __CONFIG_H */