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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
6d0f6bcf | 31 | #define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */ |
c609719b WD |
32 | #define CONFIG_ETHER_PORT_MII /* use two MII ports */ |
33 | #define CONFIG_INTEL_LXT97X /* Intel LXT97X phy */ | |
34 | ||
35 | #ifndef __ASSEMBLY__ | |
36 | #include <galileo/core.h> | |
37 | #endif | |
38 | ||
39 | #include "../board/evb64260/local.h" | |
40 | ||
41 | #define CONFIG_EVB64260 1 /* this is an EVB64260 board */ | |
42 | #define CONFIG_ZUMA_V2 1 /* always define this for ZUMA v2 */ | |
43 | ||
2ae18241 WD |
44 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
45 | ||
c609719b WD |
46 | /* #define CONFIG_ZUMA_V2_OLD 1 */ /* backwards compat for old V2 board */ |
47 | ||
48 | #define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ | |
49 | ||
50 | #define CONFIG_ECC /* enable ECC support */ | |
51 | ||
52 | #define CONFIG_750CX /* we have a 750CX/CXe (override local.h) */ | |
53 | ||
54 | /* which initialization functions to call for this board */ | |
55 | #define CONFIG_MISC_INIT_R | |
c837dcb1 | 56 | #define CONFIG_BOARD_EARLY_INIT_F |
6d0f6bcf | 57 | #define CONFIG_SYS_BOARD_ASM_INIT |
c609719b | 58 | |
6d0f6bcf | 59 | #define CONFIG_SYS_BOARD_NAME "Zuma APv2" |
c609719b | 60 | |
6d0f6bcf JCPV |
61 | #define CONFIG_SYS_HUSH_PARSER |
62 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
c609719b WD |
63 | |
64 | /* | |
65 | * The following defines let you select what serial you want to use | |
66 | * for your console driver. | |
67 | * | |
68 | * what to do: | |
69 | * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial | |
6d0f6bcf | 70 | * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 |
c609719b WD |
71 | * to 0 below. |
72 | * | |
73 | * to use the MPSC, #define CONFIG_MPSC. If you have wired up another | |
74 | * mpsc channel, change CONFIG_MPSC_PORT to the desired value. | |
75 | */ | |
76 | #define CONFIG_MPSC | |
77 | ||
78 | #define CONFIG_MPSC_PORT 0 | |
79 | ||
80 | #define CONFIG_NET_MULTI /* attempt all available adapters */ | |
81 | ||
82 | /* define this if you want to enable GT MAC filtering */ | |
83 | #define CONFIG_GT_USE_MAC_HASH_TABLE | |
84 | ||
85 | #if 1 | |
86 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
87 | #else | |
88 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
89 | #endif | |
90 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
91 | ||
92 | #undef CONFIG_BOOTARGS | |
93 | ||
94 | #define CONFIG_BOOTCOMMAND \ | |
95 | "tftpboot && " \ | |
96 | "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ | |
97 | "ip=$ipaddr:$serverip:$gatewayip:" \ | |
98 | "$netmask:$hostname:eth0:none panic=5 && bootm" | |
99 | ||
100 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ | |
6d0f6bcf | 101 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ |
c609719b WD |
102 | |
103 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
104 | #undef CONFIG_ALTIVEC /* undef to disable */ | |
105 | ||
37d4bb70 JL |
106 | /* |
107 | * BOOTP options | |
108 | */ | |
109 | #define CONFIG_BOOTP_SUBNETMASK | |
110 | #define CONFIG_BOOTP_GATEWAY | |
111 | #define CONFIG_BOOTP_HOSTNAME | |
112 | #define CONFIG_BOOTP_BOOTPATH | |
113 | #define CONFIG_BOOTP_BOOTFILESIZE | |
c609719b WD |
114 | |
115 | #define CONFIG_MII /* enable MII commands */ | |
116 | ||
a5562901 JL |
117 | |
118 | /* | |
119 | * Command line configuration. | |
120 | */ | |
121 | #include <config_cmd_default.h> | |
122 | ||
123 | #define CONFIG_CMD_ASKENV | |
124 | #define CONFIG_CMD_BSP | |
125 | #define CONFIG_CMD_JFFS2 | |
126 | #define CONFIG_CMD_MII | |
127 | #define CONFIG_CMD_DATE | |
128 | ||
c609719b | 129 | |
700a0c64 WD |
130 | /* |
131 | * JFFS2 partitions | |
132 | * | |
133 | */ | |
134 | /* No command line, one static partition, whole device */ | |
68d7d651 | 135 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
136 | #define CONFIG_JFFS2_DEV "nor0" |
137 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
138 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
139 | ||
140 | /* mtdparts command line support */ | |
141 | /* Note: fake mtd_id used, no linux mtd map file */ | |
142 | /* | |
68d7d651 | 143 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
144 | #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" |
145 | #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" | |
146 | */ | |
c609719b | 147 | |
c609719b WD |
148 | /* |
149 | * Miscellaneous configurable options | |
150 | */ | |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
152 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
a5562901 | 153 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 154 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
c609719b | 155 | #else |
6d0f6bcf | 156 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
c609719b | 157 | #endif |
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
159 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
160 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
c609719b | 161 | |
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ |
163 | #define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ | |
c609719b | 164 | |
6d0f6bcf | 165 | #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ |
c609719b | 166 | |
6d0f6bcf | 167 | #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ |
c609719b | 168 | |
ee80fa7b | 169 | #define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */ |
c609719b | 170 | |
6d0f6bcf | 171 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
c609719b WD |
172 | |
173 | /* | |
174 | * Low Level Configuration Settings | |
175 | * (address mappings, register initial values, etc.) | |
176 | * You should know what you are doing if you make changes here. | |
177 | */ | |
178 | ||
179 | /*----------------------------------------------------------------------- | |
180 | * Definitions for initial stack pointer and data area | |
181 | */ | |
6d0f6bcf | 182 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 |
553f0982 | 183 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
25ddd1fb | 184 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 185 | #define CONFIG_SYS_INIT_RAM_LOCK |
c609719b WD |
186 | |
187 | ||
188 | /*----------------------------------------------------------------------- | |
189 | * Start addresses for the final memory configuration | |
190 | * (Set up by the startup code) | |
6d0f6bcf | 191 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 192 | */ |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
194 | #define CONFIG_SYS_FLASH_BASE 0xfff00000 | |
195 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 | |
196 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
197 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
198 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ | |
c609719b WD |
199 | |
200 | /* areas to map different things with the GT in physical space */ | |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_DRAM_BANKS 4 |
202 | #define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ | |
c609719b WD |
203 | |
204 | /* What to put in the bats. */ | |
6d0f6bcf | 205 | #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 |
c609719b WD |
206 | |
207 | /* Peripheral Device section */ | |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_GT_REGS 0xf8000000 /* later mapped GT_REGS */ |
209 | #define CONFIG_SYS_DEV_BASE 0xf0000000 | |
210 | #define CONFIG_SYS_DEV0_SIZE _64M /* zuma flash @ 0xf000.0000*/ | |
211 | #define CONFIG_SYS_DEV1_SIZE _8M /* zuma IDE @ 0xf400.0000 */ | |
212 | #define CONFIG_SYS_DEV2_SIZE _8M /* unused */ | |
213 | #define CONFIG_SYS_DEV3_SIZE _8M /* unused */ | |
214 | ||
215 | #define CONFIG_SYS_DEV0_PAR 0xc498243c | |
c609719b WD |
216 | /* c 4 9 8 2 4 3 c */ |
217 | /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ | |
218 | /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ | |
219 | /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */ | |
220 | /* 3| 0|.... ..| 1| 4 | 0 | 4 | 8 | 7 | 4 */ | |
221 | ||
6d0f6bcf | 222 | #define CONFIG_SYS_DEV1_PAR 0xc01b6ac5 |
c609719b WD |
223 | /* c 0 1 b 6 a c 5 */ |
224 | /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ | |
225 | /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ | |
226 | /* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */ | |
227 | /* 3| 0|.... ..| 1| 5 | 5 | 5 | 5 | 8 | 5 */ | |
228 | ||
229 | ||
6d0f6bcf | 230 | #define CONFIG_SYS_8BIT_BOOT_PAR 0xc00b5e7c |
c609719b | 231 | |
6d0f6bcf JCPV |
232 | #define CONFIG_SYS_MPP_CONTROL_0 0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */ |
233 | #define CONFIG_SYS_MPP_CONTROL_1 0x00000000 /* GPP[15:12] : GPP[11:8] */ | |
234 | #define CONFIG_SYS_MPP_CONTROL_2 0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */ | |
235 | #define CONFIG_SYS_MPP_CONTROL_3 0x00000000 /* GPP[31:28] (int[3:0]) */ | |
c609719b WD |
236 | /* GPP[27:24] (27 is int4, rest are GPP) */ |
237 | ||
6d0f6bcf JCPV |
238 | #define CONFIG_SYS_SERIAL_PORT_MUX 0x00001101 /* 11=MPSC1/MPSC0 01=ETH, 0=only MII */ |
239 | #define CONFIG_SYS_GPP_LEVEL_CONTROL 0xf8000000 /* interrupt inputs: GPP[31:27] */ | |
c609719b | 240 | |
6d0f6bcf | 241 | #define CONFIG_SYS_SDRAM_CONFIG 0xe4e18200 /* 0x448 */ |
c609719b WD |
242 | /* idmas use buffer 1,1 |
243 | comm use buffer 1 | |
244 | pci use buffer 0,0 (pci1->0 pci0->0) | |
245 | cpu use buffer 1 (R*18) | |
246 | normal load (see also ifdef HVL) | |
247 | standard SDRAM (see also ifdef REG) | |
248 | non staggered refresh */ | |
249 | /* 31:26 25 23 20 19 18 16 */ | |
250 | /* 111001 00 111 0 0 00 1 */ | |
251 | ||
252 | /* refresh count=0x200 | |
253 | phy interleave disable (by default, | |
254 | set later by dram config..) | |
255 | virt interleave enable */ | |
256 | /* 15 14 13:0 */ | |
257 | /* 1 0 0x200 */ | |
258 | ||
6d0f6bcf JCPV |
259 | #define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE |
260 | #define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) | |
261 | #define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) | |
262 | #define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) | |
c609719b WD |
263 | |
264 | /*----------------------------------------------------------------------- | |
265 | * PCI stuff | |
266 | */ | |
267 | ||
268 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ | |
269 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
270 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
271 | ||
272 | #define CONFIG_PCI /* include pci support */ | |
273 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
274 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
275 | ||
276 | /* PCI MEMORY MAP section */ | |
6d0f6bcf JCPV |
277 | #define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 |
278 | #define CONFIG_SYS_PCI0_MEM_SIZE _128M | |
279 | #define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 | |
280 | #define CONFIG_SYS_PCI1_MEM_SIZE _128M | |
c609719b | 281 | |
6d0f6bcf JCPV |
282 | #define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) |
283 | #define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) | |
c609719b WD |
284 | |
285 | /* PCI I/O MAP section */ | |
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 |
287 | #define CONFIG_SYS_PCI0_IO_SIZE _16M | |
288 | #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 | |
289 | #define CONFIG_SYS_PCI1_IO_SIZE _16M | |
c609719b | 290 | |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) |
292 | #define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 | |
293 | #define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) | |
294 | #define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 | |
c609719b WD |
295 | |
296 | ||
297 | /*---------------------------------------------------------------------- | |
298 | * Initial BAT mappings | |
299 | */ | |
300 | ||
301 | /* NOTES: | |
302 | * 1) GUARDED and WRITE_THRU not allowed in IBATS | |
303 | * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT | |
304 | */ | |
305 | ||
306 | /* SDRAM */ | |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
308 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
309 | #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
310 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
c609719b WD |
311 | |
312 | /* init ram */ | |
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
314 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
315 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
316 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
c609719b WD |
317 | |
318 | /* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */ | |
6d0f6bcf JCPV |
319 | #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS |
320 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
321 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
322 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
c609719b WD |
323 | |
324 | /* GT regs, bootrom, all the devices, PCI I/O */ | |
6d0f6bcf JCPV |
325 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) |
326 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) | |
327 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
328 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
c609719b WD |
329 | |
330 | /* | |
331 | * For booting Linux, the board info and command line data | |
332 | * have to be in the first 8 MB of memory, since this is | |
333 | * the maximum mapped by the Linux kernel during initialization. | |
334 | */ | |
6d0f6bcf | 335 | #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ |
c609719b WD |
336 | |
337 | ||
338 | /*----------------------------------------------------------------------- | |
339 | * FLASH organization | |
340 | */ | |
6d0f6bcf JCPV |
341 | #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */ |
342 | #define CONFIG_SYS_MAX_FLASH_SECT 130 /* max number of sectors on one chip */ | |
c609719b | 343 | |
6d0f6bcf JCPV |
344 | #define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE0 /* extra flash at device 0 */ |
345 | #define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */ | |
c609719b | 346 | |
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
348 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
349 | #define CONFIG_SYS_FLASH_CFI 1 | |
c609719b | 350 | |
5a1aceb0 | 351 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
352 | #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
353 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ | |
354 | #define CONFIG_ENV_ADDR (0xfff80000 - CONFIG_ENV_SECT_SIZE) | |
c609719b WD |
355 | |
356 | /*----------------------------------------------------------------------- | |
357 | * Cache Configuration | |
358 | */ | |
6d0f6bcf | 359 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ |
a5562901 | 360 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 361 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
c609719b WD |
362 | #endif |
363 | ||
364 | /*----------------------------------------------------------------------- | |
365 | * L2CR setup -- make sure this is right for your board! | |
1d0350ed | 366 | * look in include/74xx_7xx.h for the defines used here |
c609719b WD |
367 | */ |
368 | ||
6d0f6bcf | 369 | #define CONFIG_SYS_L2 |
c609719b WD |
370 | |
371 | #ifdef CONFIG_750CX | |
372 | #define L2_INIT 0 | |
373 | #else | |
374 | #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ | |
375 | L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) | |
376 | #endif | |
377 | ||
378 | #define L2_ENABLE (L2_INIT | L2CR_L2E) | |
379 | ||
380 | /*------------------------------------------------------------------------ | |
381 | * Real time clock | |
382 | */ | |
383 | #define CONFIG_RTC_DS1302 | |
384 | ||
385 | ||
386 | /*------------------------------------------------------------------------ | |
387 | * Galileo I2C driver | |
388 | */ | |
389 | #define CONFIG_GT_I2C | |
390 | ||
c609719b | 391 | #endif /* __CONFIG_H */ |