[people/ms/u-boot.git] / include / configs / a320evb.h

/*
 * (C) Copyright 2009 Faraday Technology
 * Po-Yu Chuang <ratbert@faraday-tech.com>
 *
 * Configuation settings for the Faraday A320 board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/a320.h>

/*
 * mach-type definition
 */
#define MACH_TYPE_FARADAY	758
#define CONFIG_MACH_TYPE	MACH_TYPE_FARADAY

/*
 * Linux kernel tagged list
 */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS

/*
 * CPU and Board Configuration Options
 */
#undef CONFIG_SKIP_LOWLEVEL_INIT

/*
 * Power Management Unit
 */
#define CONFIG_FTPMU010_POWER

/*
 * Timer
 */

/*
 * Real Time Clock
 */
#define CONFIG_RTC_FTRTC010

/*
 * Serial console configuration
 */

/* FTUART is a high speed NS 16C550A compatible UART */
#define CONFIG_BAUDRATE			38400
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1		0x98200000
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#define CONFIG_SYS_NS16550_CLK		18432000

/*
 * Ethernet
 */
#define CONFIG_FTMAC100

#define CONFIG_BOOTDELAY	3

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PING

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_SYS_PROMPT	"A320 # "	/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */

/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE	\
	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

/* max number of command args */
#define CONFIG_SYS_MAXARGS	16

/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)

/*
 * SDRAM controller configuration
 */
#define CONFIG_SYS_FTSDMC020_TP0	(FTSDMC020_TP0_TRAS(2) |	\
					 FTSDMC020_TP0_TRP(1)  |	\
					 FTSDMC020_TP0_TRCD(1) |	\
					 FTSDMC020_TP0_TRF(3)  |	\
					 FTSDMC020_TP0_TWR(1)  |	\
					 FTSDMC020_TP0_TCL(2))

#define CONFIG_SYS_FTSDMC020_TP1	(FTSDMC020_TP1_INI_PREC(4) |	\
					 FTSDMC020_TP1_INI_REFT(8) |	\
					 FTSDMC020_TP1_REF_INTV(0x180))

#define CONFIG_SYS_FTSDMC020_BANK0_BSR	(FTSDMC020_BANK_ENABLE   |	\
					 FTSDMC020_BANK_DDW_X16  |	\
					 FTSDMC020_BANK_DSZ_256M |	\
					 FTSDMC020_BANK_MBW_32   |	\
					 FTSDMC020_BANK_SIZE_64M)

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB */

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
					GENERATED_GBL_DATA_SIZE)

/*
 * Load address and memory test area should agree with
 * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
 */
#define CONFIG_SYS_LOAD_ADDR		(PHYS_SDRAM_1 + 0x2000000)

/* memtest works on 63 MB in DRAM */
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + 0x3F00000)

#define CONFIG_SYS_TEXT_BASE		0

/*
 * Static memory controller configuration
 */

#define CONFIG_FTSMC020
#include <faraday/ftsmc020.h>

#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
				 FTSMC020_BANK_SIZE_1M            |	\
				 FTSMC020_BANK_MBW_8)

#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_RBE      |	\
				 FTSMC020_TPR_AST(3)   |	\
				 FTSMC020_TPR_CTW(3)   |	\
				 FTSMC020_TPR_ATI(0xf) |	\
				 FTSMC020_TPR_AT2(3)   |	\
				 FTSMC020_TPR_WTC(3)   |	\
				 FTSMC020_TPR_AHT(3)   |	\
				 FTSMC020_TPR_TRNA(0xf))

#define FTSMC020_BANK1_CONFIG	(FTSMC020_BANK_ENABLE             |	\
				 FTSMC020_BANK_BASE(PHYS_FLASH_2) |	\
				 FTSMC020_BANK_SIZE_32M           |	\
				 FTSMC020_BANK_MBW_32)

#define FTSMC020_BANK1_TIMING	(FTSMC020_TPR_AST(3)   |	\
				 FTSMC020_TPR_CTW(3)   |	\
				 FTSMC020_TPR_ATI(0xf) |	\
				 FTSMC020_TPR_AT2(3)   |	\
				 FTSMC020_TPR_WTC(3)   |	\
				 FTSMC020_TPR_AHT(3)   |	\
				 FTSMC020_TPR_TRNA(0xf))

#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
}

/*
 * FLASH and environment organization
 */

/* use CFI framework */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER

/* support JEDEC */
#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_FLASH_LEGACY_512Kx8

#define PHYS_FLASH_1			0x00000000
#define PHYS_FLASH_2			0x00400000
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, PHYS_FLASH_2, }

#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1

/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_BANKS	2

/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT	512

#undef CONFIG_SYS_FLASH_EMPTY_INFO

/* environments */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x60000)
#define CONFIG_ENV_SIZE			0x20000

#endif	/* __CONFIG_H */
Commit	Line	Data
43a5f0df PYC	1	/*
	2	* (C) Copyright 2009 Faraday Technology
	3	* Po-Yu Chuang <ratbert@faraday-tech.com>
	4	*
	5	* Configuation settings for the Faraday A320 board.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
43a5f0df PYC	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	#include <asm/arch/a320.h>
	14
9926fa01 YPC	15	/*
	16	* mach-type definition
	17	*/
	18	#define MACH_TYPE_FARADAY 758
	19	#define CONFIG_MACH_TYPE MACH_TYPE_FARADAY
	20
fd90b0d0 PYC	21	/*
	22	* Linux kernel tagged list
	23	*/
	24	#define CONFIG_CMDLINE_TAG
	25	#define CONFIG_SETUP_MEMORY_TAGS
	26
7899147b	27	/*
43a5f0df PYC	28	* CPU and Board Configuration Options
43a5f0df PYC	29	*/
43a5f0df PYC	30	#undef CONFIG_SKIP_LOWLEVEL_INIT
43a5f0df PYC	31
7899147b	32	/*
8dc667c9 PYC	33	* Power Management Unit
	34	*/
	35	#define CONFIG_FTPMU010_POWER
	36
7899147b	37	/*
43a5f0df PYC	38	* Timer
43a5f0df PYC	39	*/
43a5f0df	40
7899147b	41	/*
43a5f0df PYC	42	* Real Time Clock
	43	*/
	44	#define CONFIG_RTC_FTRTC010
	45
7899147b	46	/*
43a5f0df PYC	47	* Serial console configuration
	48	*/
	49
	50	/* FTUART is a high speed NS 16C550A compatible UART */
	51	#define CONFIG_BAUDRATE 38400
	52	#define CONFIG_CONS_INDEX 1
	53	#define CONFIG_SYS_NS16550
	54	#define CONFIG_SYS_NS16550_SERIAL
	55	#define CONFIG_SYS_NS16550_COM1 0x98200000
	56	#define CONFIG_SYS_NS16550_REG_SIZE -4
	57	#define CONFIG_SYS_NS16550_CLK 18432000
	58
7899147b	59	/*
43a5f0df PYC	60	* Ethernet
43a5f0df PYC	61	*/
43a5f0df PYC	62	#define CONFIG_FTMAC100
	63
	64	#define CONFIG_BOOTDELAY 3
	65
7899147b	66	/*
43a5f0df PYC	67	* Command line configuration.
	68	*/
	69	#include <config_cmd_default.h>
	70
	71	#define CONFIG_CMD_CACHE
	72	#define CONFIG_CMD_DATE
	73	#define CONFIG_CMD_PING
	74
7899147b	75	/*
43a5f0df PYC	76	* Miscellaneous configurable options
	77	*/
	78	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	79	#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
	80	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	81
	82	/* Print Buffer Size */
	83	#define CONFIG_SYS_PBSIZE \
	84	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	85
	86	/* max number of command args */
	87	#define CONFIG_SYS_MAXARGS 16
	88
	89	/* Boot Argument Buffer Size */
	90	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	91
7899147b	92	/*
43a5f0df PYC	93	* Size of malloc() pool
	94	*/
	95	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
	96
7899147b	97	/*
43a5f0df PYC	98	* SDRAM controller configuration
	99	*/
	100	#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) \| \
	101	FTSDMC020_TP0_TRP(1) \| \
	102	FTSDMC020_TP0_TRCD(1) \| \
	103	FTSDMC020_TP0_TRF(3) \| \
	104	FTSDMC020_TP0_TWR(1) \| \
	105	FTSDMC020_TP0_TCL(2))
	106
	107	#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) \| \
	108	FTSDMC020_TP1_INI_REFT(8) \| \
	109	FTSDMC020_TP1_REF_INTV(0x180))
	110
	111	#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE \| \
	112	FTSDMC020_BANK_DDW_X16 \| \
	113	FTSDMC020_BANK_DSZ_256M \| \
	114	FTSDMC020_BANK_MBW_32 \| \
	115	FTSDMC020_BANK_SIZE_64M)
	116
7899147b	117	/*
43a5f0df PYC	118	* Physical Memory Map
	119	*/
	120	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	121	#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
	122	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	123
5eb522a6 PYC	124	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	125	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
	126	GENERATED_GBL_DATA_SIZE)
	127
43a5f0df PYC	128	/*
	129	* Load address and memory test area should agree with
	130	* board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
	131	*/
5eb522a6	132	#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000)
43a5f0df PYC	133
43a5f0df PYC	134	/* memtest works on 63 MB in DRAM */
5eb522a6 PYC	135	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
	136	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000)
	137
	138	#define CONFIG_SYS_TEXT_BASE 0
43a5f0df	139
7899147b	140	/*
43a5f0df PYC	141	* Static memory controller configuration
	142	*/
	143
00d10eb0 ML	144	#define CONFIG_FTSMC020
00d10eb0 ML	145	#include <faraday/ftsmc020.h>
43a5f0df PYC	146
	147	#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE \| \
	148	FTSMC020_BANK_BASE(PHYS_FLASH_1) \| \
	149	FTSMC020_BANK_SIZE_1M \| \
	150	FTSMC020_BANK_MBW_8)
	151
	152	#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE \| \
	153	FTSMC020_TPR_AST(3) \| \
	154	FTSMC020_TPR_CTW(3) \| \
	155	FTSMC020_TPR_ATI(0xf) \| \
	156	FTSMC020_TPR_AT2(3) \| \
	157	FTSMC020_TPR_WTC(3) \| \
	158	FTSMC020_TPR_AHT(3) \| \
	159	FTSMC020_TPR_TRNA(0xf))
	160
	161	#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE \| \
	162	FTSMC020_BANK_BASE(PHYS_FLASH_2) \| \
	163	FTSMC020_BANK_SIZE_32M \| \
	164	FTSMC020_BANK_MBW_32)
	165
	166	#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) \| \
	167	FTSMC020_TPR_CTW(3) \| \
	168	FTSMC020_TPR_ATI(0xf) \| \
	169	FTSMC020_TPR_AT2(3) \| \
	170	FTSMC020_TPR_WTC(3) \| \
	171	FTSMC020_TPR_AHT(3) \| \
	172	FTSMC020_TPR_TRNA(0xf))
	173
	174	#define CONFIG_SYS_FTSMC020_CONFIGS { \
	175	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
	176	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
	177	}
	178
7899147b	179	/*
43a5f0df PYC	180	* FLASH and environment organization
	181	*/
	182
	183	/* use CFI framework */
	184	#define CONFIG_SYS_FLASH_CFI
	185	#define CONFIG_FLASH_CFI_DRIVER
	186
	187	/* support JEDEC */
	188	#define CONFIG_FLASH_CFI_LEGACY
	189	#define CONFIG_SYS_FLASH_LEGACY_512Kx8
	190
	191	#define PHYS_FLASH_1 0x00000000
	192	#define PHYS_FLASH_2 0x00400000
	193	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	194	#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
	195
	196	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
	197
	198	/* max number of memory banks */
	199	#define CONFIG_SYS_MAX_FLASH_BANKS 2
	200
	201	/* max number of sectors on one chip */
	202	#define CONFIG_SYS_MAX_FLASH_SECT 512
	203
	204	#undef CONFIG_SYS_FLASH_EMPTY_INFO
	205
	206	/* environments */
	207	#define CONFIG_ENV_IS_IN_FLASH
5eb522a6	208	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
43a5f0df PYC	209	#define CONFIG_ENV_SIZE 0x20000
	210
	211	#endif /* __CONFIG_H */