[people/ms/u-boot.git] / include / configs / a320evb.h

/*
 * (C) Copyright 2009 Faraday Technology
 * Po-Yu Chuang <ratbert@faraday-tech.com>
 *
 * Configuation settings for the Faraday A320 board.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/a320.h>

/*-----------------------------------------------------------------------
 * CPU and Board Configuration Options
 */
#undef CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff */

#undef CONFIG_SKIP_LOWLEVEL_INIT

/*-----------------------------------------------------------------------
 * Timer
 */
#define CONFIG_SYS_HZ		1000	/* timer ticks per second */

/*-----------------------------------------------------------------------
 * Real Time Clock
 */
#define CONFIG_RTC_FTRTC010

/*-----------------------------------------------------------------------
 * Serial console configuration
 */

/* FTUART is a high speed NS 16C550A compatible UART */
#define CONFIG_BAUDRATE			38400
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1		0x98200000
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#define CONFIG_SYS_NS16550_CLK		18432000

/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*-----------------------------------------------------------------------
 * Ethernet
 */
#define CONFIG_NET_MULTI
#define CONFIG_FTMAC100

#define CONFIG_BOOTDELAY	3

/*-----------------------------------------------------------------------
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PING

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_SYS_PROMPT	"A320 # "	/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */

/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE	\
	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

/* max number of command args */
#define CONFIG_SYS_MAXARGS	16

/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ	(4 * 1024)	/* IRQ stack */
#define CONFIG_STACKSIZE_FIQ	(4 * 1024)	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)

/*-----------------------------------------------------------------------
 * size in bytes reserved for initial data
*/

/*-----------------------------------------------------------------------
 * SDRAM controller configuration
 */
#define CONFIG_SYS_FTSDMC020_TP0	(FTSDMC020_TP0_TRAS(2) |	\
					 FTSDMC020_TP0_TRP(1)  |	\
					 FTSDMC020_TP0_TRCD(1) |	\
					 FTSDMC020_TP0_TRF(3)  |	\
					 FTSDMC020_TP0_TWR(1)  |	\
					 FTSDMC020_TP0_TCL(2))

#define CONFIG_SYS_FTSDMC020_TP1	(FTSDMC020_TP1_INI_PREC(4) |	\
					 FTSDMC020_TP1_INI_REFT(8) |	\
					 FTSDMC020_TP1_REF_INTV(0x180))

#define CONFIG_SYS_FTSDMC020_BANK0_BSR	(FTSDMC020_BANK_ENABLE   |	\
					 FTSDMC020_BANK_DDW_X16  |	\
					 FTSDMC020_BANK_DSZ_256M |	\
					 FTSDMC020_BANK_MBW_32   |	\
					 FTSDMC020_BANK_SIZE_64M)

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB */

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
					GENERATED_GBL_DATA_SIZE)

/*
 * Load address and memory test area should agree with
 * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
 */
#define CONFIG_SYS_LOAD_ADDR		(PHYS_SDRAM_1 + 0x2000000)

/* memtest works on 63 MB in DRAM */
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + 0x3F00000)

#define CONFIG_SYS_TEXT_BASE		0

/*-----------------------------------------------------------------------
 * Static memory controller configuration
 */

#include <asm/arch/ftsmc020.h>

#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
				 FTSMC020_BANK_SIZE_1M            |	\
				 FTSMC020_BANK_MBW_8)

#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_RBE      |	\
				 FTSMC020_TPR_AST(3)   |	\
				 FTSMC020_TPR_CTW(3)   |	\
				 FTSMC020_TPR_ATI(0xf) |	\
				 FTSMC020_TPR_AT2(3)   |	\
				 FTSMC020_TPR_WTC(3)   |	\
				 FTSMC020_TPR_AHT(3)   |	\
				 FTSMC020_TPR_TRNA(0xf))

#define FTSMC020_BANK1_CONFIG	(FTSMC020_BANK_ENABLE             |	\
				 FTSMC020_BANK_BASE(PHYS_FLASH_2) |	\
				 FTSMC020_BANK_SIZE_32M           |	\
				 FTSMC020_BANK_MBW_32)

#define FTSMC020_BANK1_TIMING	(FTSMC020_TPR_AST(3)   |	\
				 FTSMC020_TPR_CTW(3)   |	\
				 FTSMC020_TPR_ATI(0xf) |	\
				 FTSMC020_TPR_AT2(3)   |	\
				 FTSMC020_TPR_WTC(3)   |	\
				 FTSMC020_TPR_AHT(3)   |	\
				 FTSMC020_TPR_TRNA(0xf))

#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
}

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* use CFI framework */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER

/* support JEDEC */
#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_FLASH_LEGACY_512Kx8

#define PHYS_FLASH_1			0x00000000
#define PHYS_FLASH_2			0x00400000
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, PHYS_FLASH_2, }

#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1

/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_BANKS	2

/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT	512

#undef CONFIG_SYS_FLASH_EMPTY_INFO

/* environments */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x60000)
#define CONFIG_ENV_SIZE			0x20000

#endif	/* __CONFIG_H */
Commit	Line	Data
43a5f0df PYC	1	/*
	2	* (C) Copyright 2009 Faraday Technology
	3	* Po-Yu Chuang <ratbert@faraday-tech.com>
	4	*
	5	* Configuation settings for the Faraday A320 board.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	20	*/
	21
	22	#ifndef __CONFIG_H
	23	#define __CONFIG_H
	24
	25	#include <asm/arch/a320.h>
	26
	27	/*-----------------------------------------------------------------------
	28	* CPU and Board Configuration Options
	29	*/
	30	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	31
	32	#undef CONFIG_SKIP_LOWLEVEL_INIT
	33
	34	/*-----------------------------------------------------------------------
	35	* Timer
	36	*/
	37	#define CONFIG_SYS_HZ 1000 /* timer ticks per second */
	38
	39	/*-----------------------------------------------------------------------
	40	* Real Time Clock
	41	*/
	42	#define CONFIG_RTC_FTRTC010
	43
	44	/*-----------------------------------------------------------------------
	45	* Serial console configuration
	46	*/
	47
	48	/* FTUART is a high speed NS 16C550A compatible UART */
	49	#define CONFIG_BAUDRATE 38400
	50	#define CONFIG_CONS_INDEX 1
	51	#define CONFIG_SYS_NS16550
	52	#define CONFIG_SYS_NS16550_SERIAL
	53	#define CONFIG_SYS_NS16550_COM1 0x98200000
	54	#define CONFIG_SYS_NS16550_REG_SIZE -4
	55	#define CONFIG_SYS_NS16550_CLK 18432000
	56
	57	/* valid baudrates */
	58	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	59
	60	/*-----------------------------------------------------------------------
	61	* Ethernet
	62	*/
	63	#define CONFIG_NET_MULTI
	64	#define CONFIG_FTMAC100
65
66	#define CONFIG_BOOTDELAY 3
67
68	/*-----------------------------------------------------------------------
69	* Command line configuration.
70	*/
71	#include <config_cmd_default.h>
72
73	#define CONFIG_CMD_CACHE
74	#define CONFIG_CMD_DATE
75	#define CONFIG_CMD_PING
76
77	/*-----------------------------------------------------------------------
78	* Miscellaneous configurable options
79	*/
80	#define CONFIG_SYS_LONGHELP /* undef to save memory */
81	#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
82	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
83
84	/* Print Buffer Size */
85	#define CONFIG_SYS_PBSIZE \
86	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
87
88	/* max number of command args */
89	#define CONFIG_SYS_MAXARGS 16
90
91	/* Boot Argument Buffer Size */
92	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
93
94	/*-----------------------------------------------------------------------
95	* Stack sizes
96	*
97	* The stack sizes are set up in start.S using the settings below
98	*/
99	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
100	#ifdef CONFIG_USE_IRQ
101	#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
102	#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
103	#endif
104
105	/*-----------------------------------------------------------------------
106	* Size of malloc() pool
107	*/
108	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
109
110	/*-----------------------------------------------------------------------
111	* size in bytes reserved for initial data
112	*/
43a5f0df PYC	113
	114	/*-----------------------------------------------------------------------
	115	* SDRAM controller configuration
	116	*/
	117	#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) \| \
	118	FTSDMC020_TP0_TRP(1) \| \
	119	FTSDMC020_TP0_TRCD(1) \| \
	120	FTSDMC020_TP0_TRF(3) \| \
	121	FTSDMC020_TP0_TWR(1) \| \
	122	FTSDMC020_TP0_TCL(2))
	123
	124	#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) \| \
	125	FTSDMC020_TP1_INI_REFT(8) \| \
	126	FTSDMC020_TP1_REF_INTV(0x180))
	127
	128	#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE \| \
	129	FTSDMC020_BANK_DDW_X16 \| \
	130	FTSDMC020_BANK_DSZ_256M \| \
	131	FTSDMC020_BANK_MBW_32 \| \
	132	FTSDMC020_BANK_SIZE_64M)
	133
	134	/*-----------------------------------------------------------------------
	135	* Physical Memory Map
	136	*/
	137	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	138	#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
	139	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	140
5eb522a6 PYC	141	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	142	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
	143	GENERATED_GBL_DATA_SIZE)
	144
43a5f0df PYC	145	/*
	146	* Load address and memory test area should agree with
	147	* board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
	148	*/
5eb522a6	149	#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000)
43a5f0df PYC	150
43a5f0df PYC	151	/* memtest works on 63 MB in DRAM */
5eb522a6 PYC	152	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
	153	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000)
	154
	155	#define CONFIG_SYS_TEXT_BASE 0
43a5f0df PYC	156
	157	/*-----------------------------------------------------------------------
	158	* Static memory controller configuration
	159	*/
	160
	161	#include <asm/arch/ftsmc020.h>
	162
	163	#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE \| \
	164	FTSMC020_BANK_BASE(PHYS_FLASH_1) \| \
	165	FTSMC020_BANK_SIZE_1M \| \
	166	FTSMC020_BANK_MBW_8)
	167
	168	#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE \| \
	169	FTSMC020_TPR_AST(3) \| \
	170	FTSMC020_TPR_CTW(3) \| \
	171	FTSMC020_TPR_ATI(0xf) \| \
	172	FTSMC020_TPR_AT2(3) \| \
	173	FTSMC020_TPR_WTC(3) \| \
	174	FTSMC020_TPR_AHT(3) \| \
	175	FTSMC020_TPR_TRNA(0xf))
	176
	177	#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE \| \
	178	FTSMC020_BANK_BASE(PHYS_FLASH_2) \| \
	179	FTSMC020_BANK_SIZE_32M \| \
	180	FTSMC020_BANK_MBW_32)
	181
	182	#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) \| \
	183	FTSMC020_TPR_CTW(3) \| \
	184	FTSMC020_TPR_ATI(0xf) \| \
	185	FTSMC020_TPR_AT2(3) \| \
	186	FTSMC020_TPR_WTC(3) \| \
	187	FTSMC020_TPR_AHT(3) \| \
	188	FTSMC020_TPR_TRNA(0xf))
	189
	190	#define CONFIG_SYS_FTSMC020_CONFIGS { \
	191	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
	192	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
	193	}
	194
	195	/*-----------------------------------------------------------------------
	196	* FLASH and environment organization
	197	*/
	198
	199	/* use CFI framework */
	200	#define CONFIG_SYS_FLASH_CFI
	201	#define CONFIG_FLASH_CFI_DRIVER
	202
	203	/* support JEDEC */
	204	#define CONFIG_FLASH_CFI_LEGACY
	205	#define CONFIG_SYS_FLASH_LEGACY_512Kx8
	206
	207	#define PHYS_FLASH_1 0x00000000
	208	#define PHYS_FLASH_2 0x00400000
	209	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	210	#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
	211
	212	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
	213
	214	/* max number of memory banks */
	215	#define CONFIG_SYS_MAX_FLASH_BANKS 2
	216
	217	/* max number of sectors on one chip */
	218	#define CONFIG_SYS_MAX_FLASH_SECT 512
	219
220	#undef CONFIG_SYS_FLASH_EMPTY_INFO
221
222	/* environments */
223	#define CONFIG_ENV_IS_IN_FLASH
5eb522a6	224	#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
43a5f0df PYC	225	#define CONFIG_ENV_SIZE 0x20000
	226
	227	#endif /* __CONFIG_H */