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Commit | Line | Data |
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16c0cc1c SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /************************************************************************ | |
25 | * acadia.h - configuration for AMCC Acadia (405EZ) | |
26 | ***********************************************************************/ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /*----------------------------------------------------------------------- | |
32 | * High Level Configuration Options | |
33 | *----------------------------------------------------------------------*/ | |
3cb86f3e SR |
34 | #define CONFIG_ACADIA 1 /* Board is Acadia */ |
35 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
36 | #define CONFIG_405EZ 1 /* Specifc 405EZ support*/ | |
5d4a1790 SR |
37 | /* Detect Acadia PLL input clock automatically via CPLD bit */ |
38 | #define CONFIG_SYS_CLK_FREQ ((in8(CFG_CPLD_BASE + 0) == 0x0c) ? \ | |
39 | 66666666 : 33333000) | |
16c0cc1c | 40 | |
3cb86f3e SR |
41 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
42 | #define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */ | |
16c0cc1c SR |
43 | |
44 | #define CONFIG_NO_SERIAL_EEPROM | |
45 | /*#undef CONFIG_NO_SERIAL_EEPROM*/ | |
46 | ||
47 | #ifdef CONFIG_NO_SERIAL_EEPROM | |
16c0cc1c SR |
48 | /*---------------------------------------------------------------------------- |
49 | * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, | |
50 | * assuming a 66MHz input clock to the 405EZ. | |
51 | *---------------------------------------------------------------------------*/ | |
52 | /* #define PLLMR0_100_100_12 */ | |
53 | #define PLLMR0_200_133_66 | |
54 | /* #define PLLMR0_266_160_80 */ | |
55 | /* #define PLLMR0_333_166_83 */ | |
56 | #endif | |
57 | ||
58 | /*----------------------------------------------------------------------- | |
59 | * Base addresses -- Note these are effective addresses where the | |
60 | * actual resources get mapped (not physical addresses) | |
61 | *----------------------------------------------------------------------*/ | |
16c0cc1c | 62 | #define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */ |
3cb86f3e SR |
63 | #define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */ |
64 | ||
65 | #define CFG_SDRAM_BASE 0x00000000 | |
66 | #define CFG_FLASH_BASE 0xfe000000 | |
16c0cc1c | 67 | #define CFG_MONITOR_BASE TEXT_BASE |
3cb86f3e SR |
68 | #define CFG_CPLD_BASE 0x80000000 |
69 | #define CFG_NAND_ADDR 0xd0000000 | |
16c0cc1c SR |
70 | #define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */ |
71 | ||
3cb86f3e SR |
72 | /*----------------------------------------------------------------------- |
73 | * Initial RAM & stack pointer | |
74 | *----------------------------------------------------------------------*/ | |
75 | #define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */ | |
76 | ||
77 | /* On Chip Memory location */ | |
df8a24cd | 78 | #define CFG_OCM_DATA_ADDR 0xf8000000 |
3cb86f3e SR |
79 | #define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ |
80 | #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ | |
81 | #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ | |
82 | ||
83 | #define CFG_GBL_DATA_SIZE 128 /* size for initial data */ | |
84 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
85 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
86 | ||
87 | /*----------------------------------------------------------------------- | |
88 | * Serial Port | |
89 | *----------------------------------------------------------------------*/ | |
90 | #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ | |
91 | #define CFG_BASE_BAUD 691200 | |
92 | #define CONFIG_BAUDRATE 115200 | |
93 | #define CONFIG_SERIAL_MULTI 1 | |
94 | ||
95 | /* The following table includes the supported baudrates */ | |
96 | #define CFG_BAUDRATE_TABLE \ | |
97 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} | |
98 | ||
99 | /*----------------------------------------------------------------------- | |
100 | * Environment | |
101 | *----------------------------------------------------------------------*/ | |
16c0cc1c | 102 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
3cb86f3e | 103 | #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
16c0cc1c | 104 | #else |
3cb86f3e SR |
105 | #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ |
106 | #define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ | |
16c0cc1c SR |
107 | #endif |
108 | ||
3cb86f3e SR |
109 | /*----------------------------------------------------------------------- |
110 | * FLASH related | |
111 | *----------------------------------------------------------------------*/ | |
c440bfe6 | 112 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
3cb86f3e SR |
113 | #define CFG_FLASH_CFI /* The flash is CFI compatible */ |
114 | #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
115 | ||
116 | #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} | |
117 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
118 | #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
119 | ||
120 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
121 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
122 | ||
123 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
124 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
125 | ||
c440bfe6 SR |
126 | #else |
127 | #define CFG_NO_FLASH 1 /* No NOR on Acadia when NAND-booting */ | |
c440bfe6 SR |
128 | #endif |
129 | ||
3cb86f3e SR |
130 | #ifdef CFG_ENV_IS_IN_FLASH |
131 | #define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ | |
132 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) | |
133 | #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
134 | ||
135 | /* Address and size of Redundant Environment Sector */ | |
136 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) | |
137 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
138 | #endif | |
139 | ||
c440bfe6 SR |
140 | /* |
141 | * IPL (Initial Program Loader, integrated inside CPU) | |
142 | * Will load first 4k from NAND (SPL) into cache and execute it from there. | |
143 | * | |
144 | * SPL (Secondary Program Loader) | |
145 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL | |
146 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM | |
147 | * controller and the NAND controller so that the special U-Boot image can be | |
148 | * loaded from NAND to SDRAM. | |
149 | * | |
150 | * NUB (NAND U-Boot) | |
151 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started | |
152 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. | |
153 | * | |
154 | * On 440EPx the SPL is copied to SDRAM before the NAND controller is | |
155 | * set up. While still running from cache, I experienced problems accessing | |
156 | * the NAND controller. sr - 2006-08-25 | |
157 | */ | |
158 | #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ | |
159 | #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ | |
df8a24cd | 160 | #define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/ |
c440bfe6 SR |
161 | #define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ |
162 | #define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ | |
163 | #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) | |
164 | ||
165 | /* | |
166 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) | |
167 | */ | |
168 | #define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ | |
169 | #define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ | |
170 | ||
171 | /* | |
172 | * Now the NAND chip has to be defined (no autodetection used!) | |
173 | */ | |
174 | #define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */ | |
175 | #define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
176 | #define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */ | |
177 | #define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ | |
178 | #undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ | |
179 | ||
180 | #define CFG_NAND_ECCSIZE 256 | |
181 | #define CFG_NAND_ECCBYTES 3 | |
182 | #define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) | |
183 | #define CFG_NAND_OOBSIZE 16 | |
184 | #define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) | |
185 | #define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} | |
186 | ||
187 | #ifdef CFG_ENV_IS_IN_NAND | |
188 | /* | |
189 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
190 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. | |
191 | */ | |
192 | #define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE | |
193 | #define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) | |
194 | #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) | |
195 | #endif | |
196 | ||
3cb86f3e SR |
197 | /*----------------------------------------------------------------------- |
198 | * RAM (CRAM) | |
199 | *----------------------------------------------------------------------*/ | |
200 | #define CFG_MBYTES_RAM 64 /* 64MB */ | |
201 | ||
202 | /*----------------------------------------------------------------------- | |
203 | * I2C | |
204 | *----------------------------------------------------------------------*/ | |
205 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
206 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
207 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
208 | #define CFG_I2C_SLAVE 0x7F | |
209 | ||
210 | #define CFG_I2C_MULTI_EEPROMS | |
211 | #define CFG_I2C_EEPROM_ADDR (0xa8>>1) | |
212 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
213 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
214 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 | |
215 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
216 | ||
217 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ | |
218 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ | |
219 | #define CONFIG_DTT_AD7414 1 /* use AD7414 */ | |
220 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
221 | #define CFG_DTT_MAX_TEMP 70 | |
222 | #define CFG_DTT_LOW_TEMP -30 | |
223 | #define CFG_DTT_HYSTERESIS 3 | |
224 | ||
225 | #if 0 /* test-only... */ | |
226 | /*----------------------------------------------------------------------- | |
227 | * SPI stuff - Define to include SPI control | |
228 | *----------------------------------------------------------------------- | |
229 | */ | |
230 | #define CONFIG_SPI | |
231 | #endif | |
232 | ||
233 | /*----------------------------------------------------------------------- | |
234 | * Ethernet | |
235 | *----------------------------------------------------------------------*/ | |
236 | #define CONFIG_MII 1 /* MII PHY management */ | |
237 | #define CONFIG_PHY_ADDR 0 /* PHY address */ | |
238 | #define CONFIG_NET_MULTI 1 | |
239 | #define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/ | |
240 | ||
241 | #define CONFIG_NETCONSOLE /* include NetConsole support */ | |
242 | ||
16c0cc1c SR |
243 | #define CONFIG_PREBOOT "echo;" \ |
244 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
245 | "echo" | |
246 | ||
247 | #undef CONFIG_BOOTARGS | |
248 | ||
249 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
250 | "netdev=eth0\0" \ | |
251 | "hostname=acadia\0" \ | |
252 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
253 | "nfsroot=${serverip}:${rootpath}\0" \ | |
254 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
255 | "addip=setenv bootargs ${bootargs} " \ | |
256 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
257 | ":${hostname}:${netdev}:off panic=1\0" \ | |
258 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
259 | "flash_nfs=run nfsargs addip addtty;" \ | |
260 | "bootm ${kernel_addr}\0" \ | |
261 | "flash_self=run ramargs addip addtty;" \ | |
262 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
263 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
264 | "bootm\0" \ | |
265 | "rootpath=/opt/eldk/ppc_4xx\0" \ | |
266 | "bootfile=acadia/uImage\0" \ | |
267 | "kernel_addr=fff10000\0" \ | |
268 | "ramdisk_addr=fff20000\0" \ | |
269 | "initrd_high=30000000\0" \ | |
270 | "load=tftp 200000 acadia/u-boot.bin\0" \ | |
271 | "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ | |
272 | "cp.b ${fileaddr} fffc0000 ${filesize};" \ | |
273 | "setenv filesize;saveenv\0" \ | |
c440bfe6 SR |
274 | "upd=run load update\0" \ |
275 | "nload=tftp 200000 acadia/u-boot-nand.bin\0" \ | |
276 | "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \ | |
277 | "setenv filesize;saveenv\0" \ | |
278 | "nupd=run nload nupdate\0" \ | |
16c0cc1c SR |
279 | "kozio=bootm ffc60000\0" \ |
280 | "" | |
281 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
282 | ||
283 | #if 0 | |
284 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
285 | #else | |
286 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
287 | #endif | |
288 | ||
289 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
290 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
291 | ||
16c0cc1c SR |
292 | #define CONFIG_USB_OHCI |
293 | #define CONFIG_USB_STORAGE | |
294 | ||
16c0cc1c SR |
295 | /* Partitions */ |
296 | #define CONFIG_MAC_PARTITION | |
297 | #define CONFIG_DOS_PARTITION | |
298 | #define CONFIG_ISO_PARTITION | |
299 | ||
300 | #define CONFIG_SUPPORT_VFAT | |
301 | ||
079a136c JL |
302 | /* |
303 | * BOOTP options | |
304 | */ | |
305 | #define CONFIG_BOOTP_BOOTFILESIZE | |
306 | #define CONFIG_BOOTP_BOOTPATH | |
307 | #define CONFIG_BOOTP_GATEWAY | |
308 | #define CONFIG_BOOTP_HOSTNAME | |
309 | ||
310 | ||
0b361c91 JL |
311 | /* |
312 | * Command line configuration. | |
313 | */ | |
314 | #include <config_cmd_default.h> | |
315 | ||
316 | #define CONFIG_CMD_ASKENV | |
317 | #define CONFIG_CMD_DHCP | |
318 | #define CONFIG_CMD_DTT | |
319 | #define CONFIG_CMD_DIAG | |
320 | #define CONFIG_CMD_EEPROM | |
321 | #define CONFIG_CMD_ELF | |
322 | #define CONFIG_CMD_FAT | |
323 | #define CONFIG_CMD_I2C | |
324 | #define CONFIG_CMD_IRQ | |
325 | #define CONFIG_CMD_MII | |
326 | #define CONFIG_CMD_NAND | |
327 | #define CONFIG_CMD_NET | |
328 | #define CONFIG_CMD_NFS | |
329 | #define CONFIG_CMD_PCI | |
330 | #define CONFIG_CMD_PING | |
331 | #define CONFIG_CMD_REGINFO | |
332 | #define CONFIG_CMD_USB | |
333 | ||
334 | /* | |
335 | * No NOR on Acadia when NAND-booting | |
336 | */ | |
337 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) | |
338 | #undef CONFIG_CMD_FLASH | |
339 | #undef CONFIG_CMD_IMLS | |
340 | #endif | |
341 | ||
16c0cc1c SR |
342 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
343 | ||
3cb86f3e | 344 | /*----------------------------------------------------------------------- |
16c0cc1c | 345 | * Miscellaneous configurable options |
3cb86f3e | 346 | *----------------------------------------------------------------------*/ |
16c0cc1c | 347 | #define CFG_LONGHELP /* undef to save memory */ |
3cb86f3e | 348 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
0b361c91 | 349 | #if defined(CONFIG_CMD_KGDB) |
3cb86f3e | 350 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
16c0cc1c | 351 | #else |
3cb86f3e | 352 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
16c0cc1c | 353 | #endif |
3cb86f3e SR |
354 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
355 | #define CFG_MAXARGS 16 /* max number of command args */ | |
356 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
16c0cc1c | 357 | |
3cb86f3e SR |
358 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
359 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
16c0cc1c | 360 | |
3cb86f3e | 361 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ |
16c0cc1c SR |
362 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
363 | ||
3cb86f3e | 364 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
16c0cc1c SR |
365 | |
366 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
3cb86f3e SR |
367 | #define CONFIG_LOOPW 1 /* enable loopw command */ |
368 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
16c0cc1c SR |
369 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
370 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
371 | ||
16c0cc1c SR |
372 | /* |
373 | * For booting Linux, the board info and command line data | |
374 | * have to be in the first 8 MB of memory, since this is | |
375 | * the maximum mapped by the Linux kernel during initialization. | |
376 | */ | |
377 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
378 | ||
16c0cc1c SR |
379 | /*----------------------------------------------------------------------- |
380 | * NAND FLASH | |
381 | *----------------------------------------------------------------------*/ | |
382 | #define CFG_MAX_NAND_DEVICE 1 | |
383 | #define NAND_MAX_CHIPS 1 | |
3cb86f3e | 384 | #define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) |
16c0cc1c | 385 | #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ |
16c0cc1c SR |
386 | |
387 | /*----------------------------------------------------------------------- | |
388 | * Cache Configuration | |
389 | */ | |
390 | #define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */ | |
391 | #define CFG_CACHELINE_SIZE 32 /* ... */ | |
0b361c91 | 392 | #if defined(CONFIG_CMD_KGDB) |
16c0cc1c SR |
393 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ |
394 | #endif | |
395 | ||
16c0cc1c SR |
396 | /*----------------------------------------------------------------------- |
397 | * External Bus Controller (EBC) Setup | |
3cb86f3e | 398 | *----------------------------------------------------------------------*/ |
c440bfe6 SR |
399 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
400 | #define CFG_NAND_CS 3 | |
3cb86f3e | 401 | /* Memory Bank 0 (Flash) initialization */ |
16c0cc1c | 402 | #define CFG_EBC_PB0AP 0x03337200 |
3cb86f3e | 403 | #define CFG_EBC_PB0CR 0xfe0bc000 |
16c0cc1c | 404 | |
c440bfe6 SR |
405 | /* Memory Bank 3 (NAND-FLASH) initialization */ |
406 | #define CFG_EBC_PB3AP 0x018003c0 | |
407 | #define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000) | |
408 | ||
3cb86f3e SR |
409 | /* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/ |
410 | /* Memory Bank 1 (CRAM) initialization */ | |
16c0cc1c SR |
411 | #define CFG_EBC_PB1AP 0x030400c0 |
412 | #define CFG_EBC_PB1CR 0x000bc000 | |
413 | ||
3cb86f3e | 414 | /* Memory Bank 2 (CRAM) initialization */ |
16c0cc1c SR |
415 | #define CFG_EBC_PB2AP 0x030400c0 |
416 | #define CFG_EBC_PB2CR 0x020bc000 | |
c440bfe6 SR |
417 | #else |
418 | #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ | |
419 | /* Memory Bank 0 (NAND-FLASH) initialization */ | |
420 | #define CFG_EBC_PB0AP 0x018003c0 | |
421 | #define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000) | |
16c0cc1c | 422 | |
c440bfe6 SR |
423 | /* |
424 | * When NAND-booting the CRAM EBC setup must be done in sync mode, since the | |
425 | * NAND-SPL already initialized the CRAM and EBC to sync mode. | |
426 | */ | |
427 | /* Memory Bank 1 (CRAM) initialization */ | |
428 | #define CFG_EBC_PB1AP 0x9C0201C0 | |
429 | #define CFG_EBC_PB1CR 0x000bc000 | |
430 | ||
431 | /* Memory Bank 2 (CRAM) initialization */ | |
432 | #define CFG_EBC_PB2AP 0x9C0201C0 | |
433 | #define CFG_EBC_PB2CR 0x020bc000 | |
434 | #endif | |
16c0cc1c | 435 | |
3cb86f3e | 436 | /* Memory Bank 4 (CPLD) initialization */ |
16c0cc1c | 437 | #define CFG_EBC_PB4AP 0x04006000 |
3cb86f3e | 438 | #define CFG_EBC_PB4CR (CFG_CPLD_BASE | 0x18000) |
16c0cc1c SR |
439 | |
440 | #define CFG_EBC_CFG 0xf8400000 | |
441 | ||
3cb86f3e SR |
442 | /*----------------------------------------------------------------------- |
443 | * GPIO Setup | |
444 | *----------------------------------------------------------------------*/ | |
445 | #define CFG_GPIO_CRAM_CLK 8 | |
c440bfe6 | 446 | #define CFG_GPIO_CRAM_WAIT 9 /* GPIO-In */ |
3cb86f3e | 447 | #define CFG_GPIO_CRAM_ADV 10 |
c440bfe6 | 448 | #define CFG_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */ |
3cb86f3e | 449 | |
16c0cc1c SR |
450 | /*----------------------------------------------------------------------- |
451 | * Definitions for GPIO_0 setup (PPC405EZ specific) | |
452 | * | |
5d4a1790 SR |
453 | * GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs |
454 | * GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output | |
16c0cc1c SR |
455 | * GPIO0[4] - External Bus Controller Hold Input |
456 | * GPIO0[5] - External Bus Controller Priority Input | |
457 | * GPIO0[6] - External Bus Controller HLDA Output | |
458 | * GPIO0[7] - External Bus Controller Bus Request Output | |
459 | * GPIO0[8] - CRAM Clk Output | |
460 | * GPIO0[9] - External Bus Controller Ready Input | |
461 | * GPIO0[10] - CRAM Adv Output | |
462 | * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled | |
463 | * GPIO0[25] - External DMA Request Input | |
464 | * GPIO0[26] - External DMA EOT I/O | |
465 | * GPIO0[25] - External DMA Ack_n Output | |
466 | * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs | |
467 | * GPIO0[28-30] - Trace Outputs / PWM Inputs | |
468 | * GPIO0[31] - PWM_8 I/O | |
469 | */ | |
c440bfe6 SR |
470 | #define CFG_GPIO0_TCR 0xC0A00000 |
471 | #define CFG_GPIO0_OSRL 0x50004400 | |
5d4a1790 | 472 | #define CFG_GPIO0_OSRH 0x02000055 |
c440bfe6 | 473 | #define CFG_GPIO0_ISR1L 0x00001000 |
16c0cc1c | 474 | #define CFG_GPIO0_ISR1H 0x00000055 |
5d4a1790 | 475 | #define CFG_GPIO0_TSRL 0x02000000 |
16c0cc1c SR |
476 | #define CFG_GPIO0_TSRH 0x00000055 |
477 | ||
478 | /*----------------------------------------------------------------------- | |
479 | * Definitions for GPIO_1 setup (PPC405EZ specific) | |
480 | * | |
481 | * GPIO1[0-6] - PWM_9 to PWM_15 I/O | |
482 | * GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input | |
483 | * GPIO1[8] - TS5 Output / DAC_IP_TRIG Input | |
484 | * GPIO1[9] - TS6 Output / ADC_IP_TRIG Input | |
485 | * GPIO1[10-12] - UART0 Control Inputs | |
486 | * GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input | |
487 | * GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output | |
488 | * GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input | |
489 | * GPIO1[16] - SPI_SS_1_N Output | |
490 | * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs | |
491 | */ | |
c440bfe6 | 492 | #define CFG_GPIO1_TCR 0xFFFF8414 |
16c0cc1c | 493 | #define CFG_GPIO1_OSRL 0x40000110 |
c440bfe6 | 494 | #define CFG_GPIO1_OSRH 0x55455555 |
16c0cc1c | 495 | #define CFG_GPIO1_ISR1L 0x15555445 |
c440bfe6 | 496 | #define CFG_GPIO1_ISR1H 0x00000000 |
16c0cc1c | 497 | #define CFG_GPIO1_TSRL 0x00000000 |
c440bfe6 | 498 | #define CFG_GPIO1_TSRH 0x00000000 |
16c0cc1c | 499 | |
16c0cc1c SR |
500 | /* |
501 | * Internal Definitions | |
502 | * | |
503 | * Boot Flags | |
504 | */ | |
505 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
506 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
507 | ||
0b361c91 | 508 | #if defined(CONFIG_CMD_KGDB) |
16c0cc1c SR |
509 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
510 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
511 | #endif | |
512 | ||
513 | #endif /* __CONFIG_H */ |