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bc24345e MS |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Michael Schwingen, michael@schwingen.org | |
4 | * | |
5 | * Configuration settings for the AcTux-3 board. | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
bc24345e MS |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | #define CONFIG_IXP425 1 | |
14 | #define CONFIG_ACTUX3 1 | |
15 | ||
8e807ec3 MV |
16 | #define CONFIG_MACH_TYPE 1481 |
17 | ||
bc24345e MS |
18 | #define CONFIG_DISPLAY_CPUINFO 1 |
19 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
20 | ||
930590f3 | 21 | #define CONFIG_IXP_SERIAL |
6d0f6bcf | 22 | #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 |
bc24345e MS |
23 | #define CONFIG_BAUDRATE 115200 |
24 | #define CONFIG_BOOTDELAY 3 | |
25 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
8b5ab4c1 MS |
26 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
27 | #define CONFIG_SYS_LDSCRIPT "board/actux3/u-boot.lds" | |
bc24345e MS |
28 | |
29 | /*************************************************************** | |
30 | * U-boot generic defines start here. | |
31 | ***************************************************************/ | |
bc24345e | 32 | /* Size of malloc() pool */ |
6d0f6bcf | 33 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
bc24345e MS |
34 | |
35 | /* allow to overwrite serial and ethaddr */ | |
36 | #define CONFIG_ENV_OVERWRITE | |
37 | ||
38 | /* Command line configuration. */ | |
39 | #include <config_cmd_default.h> | |
40 | ||
41 | #define CONFIG_CMD_ELF | |
42 | ||
43 | #define CONFIG_BOOTCOMMAND "run boot_flash" | |
44 | /* enable passing of ATAGs */ | |
45 | #define CONFIG_CMDLINE_TAG 1 | |
46 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
47 | #define CONFIG_INITRD_TAG 1 | |
48 | #define CONFIG_REVISION_TAG 1 | |
49 | ||
50 | #if defined(CONFIG_CMD_KGDB) | |
51 | # define CONFIG_KGDB_BAUDRATE 230400 | |
52 | /* which serial port to use */ | |
53 | # define CONFIG_KGDB_SER_INDEX 1 | |
54 | #endif | |
55 | ||
56 | /* Miscellaneous configurable options */ | |
6d0f6bcf | 57 | #define CONFIG_SYS_LONGHELP |
bc24345e | 58 | /* Console I/O Buffer Size */ |
6d0f6bcf | 59 | #define CONFIG_SYS_CBSIZE 256 |
bc24345e | 60 | /* Print Buffer Size */ |
6d0f6bcf | 61 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
bc24345e | 62 | /* max number of command args */ |
6d0f6bcf | 63 | #define CONFIG_SYS_MAXARGS 16 |
bc24345e | 64 | /* Boot Argument Buffer Size */ |
6d0f6bcf | 65 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
bc24345e | 66 | |
6d0f6bcf JCPV |
67 | #define CONFIG_SYS_MEMTEST_START 0x00400000 |
68 | #define CONFIG_SYS_MEMTEST_END 0x00800000 | |
bc24345e | 69 | |
8b5ab4c1 MS |
70 | /* timer clock - 2* OSC_IN system clock */ |
71 | #define CONFIG_IXP425_TIMER_CLK 66666666 | |
bc24345e MS |
72 | |
73 | /* default load address */ | |
6d0f6bcf | 74 | #define CONFIG_SYS_LOAD_ADDR 0x00010000 |
bc24345e MS |
75 | |
76 | /* valid baudrates */ | |
6d0f6bcf | 77 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ |
bc24345e MS |
78 | 115200, 230400 } |
79 | #define CONFIG_SERIAL_RTS_ACTIVE 1 | |
80 | ||
bc24345e | 81 | /* Expansion bus settings */ |
6d0f6bcf | 82 | #define CONFIG_SYS_EXP_CS0 0xbd113442 |
bc24345e MS |
83 | |
84 | /* SDRAM settings */ | |
85 | #define CONFIG_NR_DRAM_BANKS 1 | |
86 | #define PHYS_SDRAM_1 0x00000000 | |
8b5ab4c1 | 87 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
bc24345e MS |
88 | |
89 | /* 16MB SDRAM */ | |
6d0f6bcf | 90 | #define CONFIG_SYS_SDR_CONFIG 0x3A |
bc24345e | 91 | #define PHYS_SDRAM_1_SIZE 0x01000000 |
6d0f6bcf JCPV |
92 | #define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a |
93 | #define CONFIG_SYS_SDR_MODE_CONFIG 0x1 | |
94 | #define CONFIG_SYS_DRAM_SIZE 0x01000000 | |
bc24345e MS |
95 | |
96 | /* FLASH organization */ | |
8b5ab4c1 | 97 | #define CONFIG_SYS_TEXT_BASE 0x50000000 |
6d0f6bcf | 98 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
bc24345e | 99 | /* max number of sectors on one chip */ |
6d0f6bcf | 100 | #define CONFIG_SYS_MAX_FLASH_SECT 140 |
bc24345e | 101 | #define PHYS_FLASH_1 0x50000000 |
6d0f6bcf | 102 | #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } |
bc24345e | 103 | |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
105 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 | |
106 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
8b5ab4c1 | 107 | #define CONFIG_BOARD_SIZE_LIMIT 262144 |
bc24345e MS |
108 | |
109 | /* Use common CFI driver */ | |
6d0f6bcf | 110 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 111 | #define CONFIG_FLASH_CFI_DRIVER |
bc24345e | 112 | /* no byte writes on IXP4xx */ |
6d0f6bcf | 113 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
bc24345e MS |
114 | |
115 | /* print 'E' for empty sector on flinfo */ | |
6d0f6bcf | 116 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
bc24345e MS |
117 | |
118 | /* Ethernet */ | |
119 | ||
120 | /* include IXP4xx NPE support */ | |
121 | #define CONFIG_IXP4XX_NPE 1 | |
bc24345e | 122 | |
bc24345e MS |
123 | /* NPE0 PHY address */ |
124 | #define CONFIG_PHY_ADDR 0x10 | |
125 | /* MII PHY management */ | |
126 | #define CONFIG_MII 1 | |
8b5ab4c1 MS |
127 | /* fixed-speed switch without standard PHY registers on MII */ |
128 | #define CONFIG_MII_NPE0_FIXEDLINK 1 | |
129 | #define CONFIG_MII_NPE0_SPEED 100 | |
130 | #define CONFIG_MII_NPE0_FULLDUPLEX 1 | |
131 | ||
bc24345e | 132 | /* Number of ethernet rx buffers & descriptors */ |
6d0f6bcf | 133 | #define CONFIG_SYS_RX_ETH_BUFFER 16 |
bc24345e MS |
134 | #define CONFIG_RESET_PHY_R 1 |
135 | /* ethernet switch connected to MII port */ | |
136 | #define CONFIG_MII_ETHSWITCH 1 | |
137 | ||
138 | #define CONFIG_CMD_DHCP | |
139 | #define CONFIG_CMD_NET | |
140 | #define CONFIG_CMD_MII | |
141 | #define CONFIG_CMD_PING | |
142 | #undef CONFIG_CMD_NFS | |
143 | ||
144 | /* BOOTP options */ | |
145 | #define CONFIG_BOOTP_BOOTFILESIZE | |
146 | #define CONFIG_BOOTP_BOOTPATH | |
147 | #define CONFIG_BOOTP_GATEWAY | |
148 | #define CONFIG_BOOTP_HOSTNAME | |
149 | ||
150 | /* Cache Configuration */ | |
6d0f6bcf | 151 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
bc24345e MS |
152 | |
153 | /* | |
154 | * environment organization: | |
155 | * one flash sector, embedded in uboot area (bottom bootblock flash) | |
156 | */ | |
5a1aceb0 | 157 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
158 | #define CONFIG_ENV_SIZE 0x2000 |
159 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) | |
6d0f6bcf | 160 | #define CONFIG_SYS_USE_PPCENV 1 |
bc24345e MS |
161 | |
162 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
b4e2f89d | 163 | "npe_ucode=50040000\0" \ |
bc24345e MS |
164 | "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ |
165 | "kerneladdr=50050000\0" \ | |
8b5ab4c1 MS |
166 | "kernelfile=actux3/uImage\0" \ |
167 | "rootfile=actux3/rootfs\0" \ | |
bc24345e MS |
168 | "rootaddr=50170000\0" \ |
169 | "loadaddr=10000\0" \ | |
170 | "updateboot_ser=mw.b 10000 ff 40000;" \ | |
171 | " loady ${loadaddr};" \ | |
172 | " run eraseboot writeboot\0" \ | |
173 | "updateboot_net=mw.b 10000 ff 40000;" \ | |
8b5ab4c1 | 174 | " tftp ${loadaddr} actux3/u-boot.bin;" \ |
bc24345e MS |
175 | " run eraseboot writeboot\0" \ |
176 | "eraseboot=protect off 50000000 50003fff;" \ | |
177 | " protect off 50006000 5003ffff;" \ | |
178 | " erase 50000000 50003fff;" \ | |
179 | " erase 50006000 5003ffff\0" \ | |
180 | "writeboot=cp.b 10000 50000000 4000;" \ | |
181 | " cp.b 16000 50006000 3a000\0" \ | |
8b5ab4c1 MS |
182 | "updateucode=loady;" \ |
183 | " era ${npe_ucode} +${filesize};" \ | |
184 | " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ | |
bc24345e MS |
185 | "updateroot=tftp ${loadaddr} ${rootfile};" \ |
186 | " era ${rootaddr} +${filesize};" \ | |
187 | " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ | |
188 | "updatekern=tftp ${loadaddr} ${kernelfile};" \ | |
189 | " era ${kerneladdr} +${filesize};" \ | |
190 | " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ | |
191 | "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ | |
192 | " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ | |
193 | "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ | |
194 | " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ | |
8b5ab4c1 | 195 | "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \ |
bc24345e MS |
196 | "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ |
197 | "boot_flash=run flashargs addtty addeth;" \ | |
198 | " bootm ${kerneladdr}\0" \ | |
199 | "boot_net=run netargs addtty addeth;" \ | |
200 | " tftpboot ${loadaddr} ${kernelfile};" \ | |
201 | " bootm\0" | |
202 | ||
8b5ab4c1 MS |
203 | /* additions for new relocation code, must be added to all boards */ |
204 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
205 | (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) | |
206 | ||
bc24345e | 207 | #endif /* __CONFIG_H */ |