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bc24345e MS |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Michael Schwingen, michael@schwingen.org | |
4 | * | |
5 | * Configuration settings for the AcTux-3 board. | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | #define CONFIG_IXP425 1 | |
30 | #define CONFIG_ACTUX3 1 | |
31 | ||
32 | #define CONFIG_DISPLAY_CPUINFO 1 | |
33 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
34 | ||
930590f3 | 35 | #define CONFIG_IXP_SERIAL |
6d0f6bcf | 36 | #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 |
bc24345e MS |
37 | #define CONFIG_BAUDRATE 115200 |
38 | #define CONFIG_BOOTDELAY 3 | |
39 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
8b5ab4c1 MS |
40 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
41 | #define CONFIG_SYS_LDSCRIPT "board/actux3/u-boot.lds" | |
bc24345e MS |
42 | |
43 | /*************************************************************** | |
44 | * U-boot generic defines start here. | |
45 | ***************************************************************/ | |
bc24345e | 46 | /* Size of malloc() pool */ |
6d0f6bcf | 47 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
bc24345e MS |
48 | |
49 | /* allow to overwrite serial and ethaddr */ | |
50 | #define CONFIG_ENV_OVERWRITE | |
51 | ||
52 | /* Command line configuration. */ | |
53 | #include <config_cmd_default.h> | |
54 | ||
55 | #define CONFIG_CMD_ELF | |
56 | ||
57 | #define CONFIG_BOOTCOMMAND "run boot_flash" | |
58 | /* enable passing of ATAGs */ | |
59 | #define CONFIG_CMDLINE_TAG 1 | |
60 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
61 | #define CONFIG_INITRD_TAG 1 | |
62 | #define CONFIG_REVISION_TAG 1 | |
63 | ||
64 | #if defined(CONFIG_CMD_KGDB) | |
65 | # define CONFIG_KGDB_BAUDRATE 230400 | |
66 | /* which serial port to use */ | |
67 | # define CONFIG_KGDB_SER_INDEX 1 | |
68 | #endif | |
69 | ||
70 | /* Miscellaneous configurable options */ | |
6d0f6bcf JCPV |
71 | #define CONFIG_SYS_LONGHELP |
72 | #define CONFIG_SYS_PROMPT "=> " | |
bc24345e | 73 | /* Console I/O Buffer Size */ |
6d0f6bcf | 74 | #define CONFIG_SYS_CBSIZE 256 |
bc24345e | 75 | /* Print Buffer Size */ |
6d0f6bcf | 76 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
bc24345e | 77 | /* max number of command args */ |
6d0f6bcf | 78 | #define CONFIG_SYS_MAXARGS 16 |
bc24345e | 79 | /* Boot Argument Buffer Size */ |
6d0f6bcf | 80 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
bc24345e | 81 | |
6d0f6bcf JCPV |
82 | #define CONFIG_SYS_MEMTEST_START 0x00400000 |
83 | #define CONFIG_SYS_MEMTEST_END 0x00800000 | |
bc24345e | 84 | |
8b5ab4c1 MS |
85 | /* timer clock - 2* OSC_IN system clock */ |
86 | #define CONFIG_IXP425_TIMER_CLK 66666666 | |
87 | #define CONFIG_SYS_HZ 1000 | |
bc24345e MS |
88 | |
89 | /* default load address */ | |
6d0f6bcf | 90 | #define CONFIG_SYS_LOAD_ADDR 0x00010000 |
bc24345e MS |
91 | |
92 | /* valid baudrates */ | |
6d0f6bcf | 93 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ |
bc24345e MS |
94 | 115200, 230400 } |
95 | #define CONFIG_SERIAL_RTS_ACTIVE 1 | |
96 | ||
97 | /* | |
98 | * Stack sizes | |
99 | * | |
100 | * The stack sizes are set up in start.S using the settings below | |
101 | */ | |
102 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
bc24345e MS |
103 | |
104 | /* Expansion bus settings */ | |
6d0f6bcf | 105 | #define CONFIG_SYS_EXP_CS0 0xbd113442 |
bc24345e MS |
106 | |
107 | /* SDRAM settings */ | |
108 | #define CONFIG_NR_DRAM_BANKS 1 | |
109 | #define PHYS_SDRAM_1 0x00000000 | |
8b5ab4c1 | 110 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
bc24345e MS |
111 | |
112 | /* 16MB SDRAM */ | |
6d0f6bcf | 113 | #define CONFIG_SYS_SDR_CONFIG 0x3A |
bc24345e | 114 | #define PHYS_SDRAM_1_SIZE 0x01000000 |
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a |
116 | #define CONFIG_SYS_SDR_MODE_CONFIG 0x1 | |
117 | #define CONFIG_SYS_DRAM_SIZE 0x01000000 | |
bc24345e MS |
118 | |
119 | /* FLASH organization */ | |
8b5ab4c1 | 120 | #define CONFIG_SYS_TEXT_BASE 0x50000000 |
6d0f6bcf | 121 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
bc24345e | 122 | /* max number of sectors on one chip */ |
6d0f6bcf | 123 | #define CONFIG_SYS_MAX_FLASH_SECT 140 |
bc24345e | 124 | #define PHYS_FLASH_1 0x50000000 |
6d0f6bcf | 125 | #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } |
bc24345e | 126 | |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
128 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 | |
129 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
8b5ab4c1 | 130 | #define CONFIG_BOARD_SIZE_LIMIT 262144 |
bc24345e MS |
131 | |
132 | /* Use common CFI driver */ | |
6d0f6bcf | 133 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 134 | #define CONFIG_FLASH_CFI_DRIVER |
bc24345e | 135 | /* no byte writes on IXP4xx */ |
6d0f6bcf | 136 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
bc24345e MS |
137 | |
138 | /* print 'E' for empty sector on flinfo */ | |
6d0f6bcf | 139 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
bc24345e MS |
140 | |
141 | /* Ethernet */ | |
142 | ||
143 | /* include IXP4xx NPE support */ | |
144 | #define CONFIG_IXP4XX_NPE 1 | |
bc24345e | 145 | |
bc24345e MS |
146 | /* NPE0 PHY address */ |
147 | #define CONFIG_PHY_ADDR 0x10 | |
148 | /* MII PHY management */ | |
149 | #define CONFIG_MII 1 | |
8b5ab4c1 MS |
150 | /* fixed-speed switch without standard PHY registers on MII */ |
151 | #define CONFIG_MII_NPE0_FIXEDLINK 1 | |
152 | #define CONFIG_MII_NPE0_SPEED 100 | |
153 | #define CONFIG_MII_NPE0_FULLDUPLEX 1 | |
154 | ||
bc24345e | 155 | /* Number of ethernet rx buffers & descriptors */ |
6d0f6bcf | 156 | #define CONFIG_SYS_RX_ETH_BUFFER 16 |
bc24345e MS |
157 | #define CONFIG_RESET_PHY_R 1 |
158 | /* ethernet switch connected to MII port */ | |
159 | #define CONFIG_MII_ETHSWITCH 1 | |
160 | ||
161 | #define CONFIG_CMD_DHCP | |
162 | #define CONFIG_CMD_NET | |
163 | #define CONFIG_CMD_MII | |
164 | #define CONFIG_CMD_PING | |
165 | #undef CONFIG_CMD_NFS | |
166 | ||
167 | /* BOOTP options */ | |
168 | #define CONFIG_BOOTP_BOOTFILESIZE | |
169 | #define CONFIG_BOOTP_BOOTPATH | |
170 | #define CONFIG_BOOTP_GATEWAY | |
171 | #define CONFIG_BOOTP_HOSTNAME | |
172 | ||
173 | /* Cache Configuration */ | |
6d0f6bcf | 174 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
bc24345e MS |
175 | |
176 | /* | |
177 | * environment organization: | |
178 | * one flash sector, embedded in uboot area (bottom bootblock flash) | |
179 | */ | |
5a1aceb0 | 180 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
181 | #define CONFIG_ENV_SIZE 0x2000 |
182 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) | |
6d0f6bcf | 183 | #define CONFIG_SYS_USE_PPCENV 1 |
bc24345e MS |
184 | |
185 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
b4e2f89d | 186 | "npe_ucode=50040000\0" \ |
bc24345e MS |
187 | "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ |
188 | "kerneladdr=50050000\0" \ | |
8b5ab4c1 MS |
189 | "kernelfile=actux3/uImage\0" \ |
190 | "rootfile=actux3/rootfs\0" \ | |
bc24345e MS |
191 | "rootaddr=50170000\0" \ |
192 | "loadaddr=10000\0" \ | |
193 | "updateboot_ser=mw.b 10000 ff 40000;" \ | |
194 | " loady ${loadaddr};" \ | |
195 | " run eraseboot writeboot\0" \ | |
196 | "updateboot_net=mw.b 10000 ff 40000;" \ | |
8b5ab4c1 | 197 | " tftp ${loadaddr} actux3/u-boot.bin;" \ |
bc24345e MS |
198 | " run eraseboot writeboot\0" \ |
199 | "eraseboot=protect off 50000000 50003fff;" \ | |
200 | " protect off 50006000 5003ffff;" \ | |
201 | " erase 50000000 50003fff;" \ | |
202 | " erase 50006000 5003ffff\0" \ | |
203 | "writeboot=cp.b 10000 50000000 4000;" \ | |
204 | " cp.b 16000 50006000 3a000\0" \ | |
8b5ab4c1 MS |
205 | "updateucode=loady;" \ |
206 | " era ${npe_ucode} +${filesize};" \ | |
207 | " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ | |
bc24345e MS |
208 | "updateroot=tftp ${loadaddr} ${rootfile};" \ |
209 | " era ${rootaddr} +${filesize};" \ | |
210 | " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ | |
211 | "updatekern=tftp ${loadaddr} ${kernelfile};" \ | |
212 | " era ${kerneladdr} +${filesize};" \ | |
213 | " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ | |
214 | "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ | |
215 | " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ | |
216 | "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ | |
217 | " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ | |
8b5ab4c1 | 218 | "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \ |
bc24345e MS |
219 | "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ |
220 | "boot_flash=run flashargs addtty addeth;" \ | |
221 | " bootm ${kerneladdr}\0" \ | |
222 | "boot_net=run netargs addtty addeth;" \ | |
223 | " tftpboot ${loadaddr} ${kernelfile};" \ | |
224 | " bootm\0" | |
225 | ||
8b5ab4c1 MS |
226 | /* additions for new relocation code, must be added to all boards */ |
227 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
228 | (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) | |
229 | ||
bc24345e | 230 | #endif /* __CONFIG_H */ |