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66a4344a MS |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Michael Schwingen, michael@schwingen.org | |
4 | * | |
5 | * Configuration settings for the AcTux-4 board. | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
66a4344a MS |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | #define CONFIG_IXP425 1 | |
14 | #define CONFIG_ACTUX4 1 | |
15 | ||
8e807ec3 MV |
16 | #define CONFIG_MACH_TYPE 1532 |
17 | ||
66a4344a MS |
18 | #define CONFIG_DISPLAY_CPUINFO 1 |
19 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
20 | ||
930590f3 | 21 | #define CONFIG_IXP_SERIAL |
6d0f6bcf | 22 | #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 |
66a4344a MS |
23 | #define CONFIG_BAUDRATE 115200 |
24 | #define CONFIG_BOOTDELAY 3 | |
25 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
080b7643 | 26 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
66a4344a MS |
27 | |
28 | /*************************************************************** | |
29 | * U-boot generic defines start here. | |
30 | ***************************************************************/ | |
66a4344a | 31 | /* Size of malloc() pool */ |
6d0f6bcf | 32 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
66a4344a MS |
33 | |
34 | /* allow to overwrite serial and ethaddr */ | |
35 | #define CONFIG_ENV_OVERWRITE | |
36 | ||
37 | /* Command line configuration */ | |
38 | #include <config_cmd_default.h> | |
39 | ||
40 | #define CONFIG_CMD_ELF | |
41 | ||
080b7643 MS |
42 | #define CONFIG_PCI |
43 | #ifdef CONFIG_PCI | |
44 | #define CONFIG_CMD_PCI | |
45 | #define CONFIG_PCI_PNP | |
46 | #define CONFIG_IXP_PCI | |
47 | #define CONFIG_PCI_SCAN_SHOW | |
48 | #define CONFIG_CMD_PCI_ENUM | |
49 | #endif | |
50 | ||
66a4344a MS |
51 | #define CONFIG_BOOTCOMMAND "run boot_flash" |
52 | /* enable passing of ATAGs */ | |
53 | #define CONFIG_CMDLINE_TAG 1 | |
54 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
55 | #define CONFIG_INITRD_TAG 1 | |
56 | ||
57 | #if defined(CONFIG_CMD_KGDB) | |
58 | # define CONFIG_KGDB_BAUDRATE 230400 | |
66a4344a MS |
59 | #endif |
60 | ||
61 | /* Miscellaneous configurable options */ | |
6d0f6bcf | 62 | #define CONFIG_SYS_LONGHELP |
66a4344a | 63 | /* Console I/O Buffer Size */ |
6d0f6bcf | 64 | #define CONFIG_SYS_CBSIZE 256 |
66a4344a | 65 | /* Print Buffer Size */ |
6d0f6bcf | 66 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
66a4344a | 67 | /* max number of command args */ |
6d0f6bcf | 68 | #define CONFIG_SYS_MAXARGS 16 |
66a4344a | 69 | /* Boot Argument Buffer Size */ |
6d0f6bcf | 70 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
66a4344a | 71 | |
6d0f6bcf JCPV |
72 | #define CONFIG_SYS_MEMTEST_START 0x00400000 |
73 | #define CONFIG_SYS_MEMTEST_END 0x00800000 | |
66a4344a | 74 | |
080b7643 MS |
75 | /* timer clock - 2* OSC_IN system clock */ |
76 | #define CONFIG_IXP425_TIMER_CLK 66000000 | |
66a4344a MS |
77 | |
78 | /* default load address */ | |
6d0f6bcf | 79 | #define CONFIG_SYS_LOAD_ADDR 0x00010000 |
66a4344a MS |
80 | |
81 | /* valid baudrates */ | |
6d0f6bcf | 82 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ |
66a4344a MS |
83 | 115200, 230400 } |
84 | #define CONFIG_SERIAL_RTS_ACTIVE 1 | |
85 | ||
66a4344a | 86 | /* Expansion bus settings */ |
6d0f6bcf | 87 | #define CONFIG_SYS_EXP_CS0 0xbd113003 |
66a4344a MS |
88 | |
89 | /* SDRAM settings */ | |
90 | #define CONFIG_NR_DRAM_BANKS 1 | |
91 | #define PHYS_SDRAM_1 0x00000000 | |
080b7643 | 92 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
66a4344a MS |
93 | |
94 | /* 32MB SDRAM */ | |
6d0f6bcf | 95 | #define CONFIG_SYS_SDR_CONFIG 0x18 |
66a4344a | 96 | #define PHYS_SDRAM_1_SIZE 0x02000000 |
6d0f6bcf JCPV |
97 | #define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a |
98 | #define CONFIG_SYS_SDR_MODE_CONFIG 0x1 | |
99 | #define CONFIG_SYS_DRAM_SIZE 0x02000000 | |
66a4344a MS |
100 | |
101 | /* FLASH organization */ | |
080b7643 | 102 | #define CONFIG_SYS_TEXT_BASE 0x50000000 |
6d0f6bcf | 103 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 |
66a4344a | 104 | /* max # of sectors per chip */ |
6d0f6bcf | 105 | #define CONFIG_SYS_MAX_FLASH_SECT 70 |
66a4344a MS |
106 | #define PHYS_FLASH_1 0x50000000 |
107 | #define PHYS_FLASH_2 0x51000000 | |
6d0f6bcf | 108 | #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } |
66a4344a | 109 | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
111 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 | |
112 | #define CONFIG_SYS_MONITOR_LEN (252 << 10) | |
080b7643 | 113 | #define CONFIG_BOARD_SIZE_LIMIT 258048 |
66a4344a MS |
114 | |
115 | /* Use common CFI driver */ | |
6d0f6bcf | 116 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 117 | #define CONFIG_FLASH_CFI_DRIVER |
66a4344a MS |
118 | /* board provides its own flash_init code */ |
119 | #define CONFIG_FLASH_CFI_LEGACY 1 | |
120 | /* no byte writes on IXP4xx */ | |
6d0f6bcf | 121 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
66a4344a | 122 | /* SST 39VF020 etc. support */ |
6d0f6bcf | 123 | #define CONFIG_SYS_FLASH_LEGACY_256Kx8 1 |
66a4344a MS |
124 | |
125 | /* print 'E' for empty sector on flinfo */ | |
6d0f6bcf | 126 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
66a4344a MS |
127 | |
128 | /* Ethernet */ | |
129 | ||
130 | /* include IXP4xx NPE support */ | |
131 | #define CONFIG_IXP4XX_NPE 1 | |
66a4344a | 132 | |
66a4344a MS |
133 | /* NPE0 PHY address */ |
134 | #define CONFIG_PHY_ADDR 0x1C | |
135 | /* MII PHY management */ | |
136 | #define CONFIG_MII 1 | |
080b7643 | 137 | |
66a4344a | 138 | /* Number of ethernet rx buffers & descriptors */ |
6d0f6bcf | 139 | #define CONFIG_SYS_RX_ETH_BUFFER 16 |
66a4344a MS |
140 | |
141 | #define CONFIG_CMD_DHCP | |
142 | #define CONFIG_CMD_NET | |
143 | #define CONFIG_CMD_MII | |
144 | #define CONFIG_CMD_PING | |
145 | #undef CONFIG_CMD_NFS | |
146 | ||
147 | /* BOOTP options */ | |
148 | #define CONFIG_BOOTP_BOOTFILESIZE | |
149 | #define CONFIG_BOOTP_BOOTPATH | |
150 | #define CONFIG_BOOTP_GATEWAY | |
151 | #define CONFIG_BOOTP_HOSTNAME | |
152 | ||
153 | /* Cache Configuration */ | |
6d0f6bcf | 154 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
66a4344a MS |
155 | |
156 | /* environment organization: one complete 4k flash sector */ | |
5a1aceb0 | 157 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
158 | #define CONFIG_ENV_SIZE 0x1000 |
159 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3f000) | |
66a4344a MS |
160 | |
161 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
b4e2f89d | 162 | "npe_ucode=51000000\0" \ |
66a4344a MS |
163 | "mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);" \ |
164 | "IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0" \ | |
165 | "kerneladdr=51020000\0" \ | |
080b7643 MS |
166 | "kernelfile=actux4/uImage\0" \ |
167 | "rootfile=actux4/rootfs\0" \ | |
66a4344a MS |
168 | "rootaddr=51160000\0" \ |
169 | "loadaddr=10000\0" \ | |
170 | "updateboot_ser=mw.b 10000 ff 40000;" \ | |
171 | " loady ${loadaddr};" \ | |
172 | " run eraseboot writeboot\0" \ | |
173 | "updateboot_net=mw.b 10000 ff 40000;" \ | |
080b7643 | 174 | " tftp ${loadaddr} actux4/u-boot.bin;" \ |
66a4344a MS |
175 | " run eraseboot writeboot\0" \ |
176 | "eraseboot=protect off 50000000 5003efff;" \ | |
177 | " erase 50000000 +${filesize}\0" \ | |
178 | "writeboot=cp.b 10000 50000000 ${filesize}\0" \ | |
080b7643 MS |
179 | "updateucode=loady;" \ |
180 | " era ${npe_ucode} +${filesize};" \ | |
181 | " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \ | |
66a4344a MS |
182 | "updateroot=tftp ${loadaddr} ${rootfile};" \ |
183 | " era ${rootaddr} +${filesize};" \ | |
184 | " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ | |
185 | "updatekern=tftp ${loadaddr} ${kernelfile};" \ | |
186 | " era ${kerneladdr} +${filesize};" \ | |
187 | " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ | |
188 | "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \ | |
189 | " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ | |
190 | "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \ | |
191 | " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ | |
192 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ | |
193 | "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ | |
194 | "boot_flash=run flashargs addtty addeth;" \ | |
195 | " bootm ${kerneladdr}\0" \ | |
196 | "boot_net=run netargs addtty addeth;" \ | |
197 | " tftpboot ${loadaddr} ${kernelfile};" \ | |
198 | " bootm\0" | |
199 | ||
080b7643 MS |
200 | /* additions for new relocation code, must be added to all boards */ |
201 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
202 | (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) | |
203 | ||
66a4344a | 204 | #endif /* __CONFIG_H */ |