[thirdparty/u-boot.git] / include / configs / adp-ae3xx.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2011 Andes Technology Corporation
 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch-ae3xx/ae3xx.h>

/*
 * CPU and Board Configuration Options
 */
#define CONFIG_USE_INTERRUPT

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_SKIP_TRUNOFF_WATCHDOG

#define CONFIG_ARCH_MAP_SYSMEM

#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_SERVERIP

#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#ifdef CONFIG_OF_CONTROL
#undef CONFIG_OF_SEPARATE
#define CONFIG_OF_EMBED
#endif
#endif

/*
 * Timer
 */
#define CONFIG_SYS_CLK_FREQ	39062500
#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ

/*
 * Use Externel CLOCK or PCLK
 */
#undef CONFIG_FTRTC010_EXTCLK

#ifndef CONFIG_FTRTC010_EXTCLK
#define CONFIG_FTRTC010_PCLK
#endif

#ifdef CONFIG_FTRTC010_EXTCLK
#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
#else
#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
#endif

#define TIMER_LOAD_VAL	0xffffffff

/*
 * Real Time Clock
 */
#define CONFIG_RTC_FTRTC010

/*
 * Real Time Clock Divider
 * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
 */
#define OSC_5MHZ			(5*1000000)
#define OSC_CLK				(4*OSC_5MHZ)
#define RTC_DIV_COUNT			(0.5)	/* Why?? */

/*
 * Serial console configuration
 */

/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#endif
#define CONFIG_SYS_NS16550_CLK		((18432000 * 20) / 25)	/* AG101P */

/*
 * Miscellaneous configurable options
 */

/*
 * Size of malloc() pool
 */
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
#define CONFIG_SYS_MALLOC_LEN		(512 << 10)

/*
 * Physical Memory Map
 */
#define PHYS_SDRAM_0	0x00000000  /* SDRAM Bank #1 */

#define PHYS_SDRAM_1 \
	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */

#define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
					GENERATED_GBL_DATA_SIZE)

/*
 * Load address and memory test area should agree with
 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
 */
#define CONFIG_SYS_LOAD_ADDR		0x300000

/* memtest works on 63 MB in DRAM */

/*
 * Static memory controller configuration
 */
#define CONFIG_FTSMC020

#ifdef CONFIG_FTSMC020
#include <faraday/ftsmc020.h>

#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
}

#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
					 FTSMC020_BANK_SIZE_32M	|	\
					 FTSMC020_BANK_MBW_32)

#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
					 FTSMC020_TPR_AST(1)	|	\
					 FTSMC020_TPR_CTW(1)	|	\
					 FTSMC020_TPR_ATI(1)	|	\
					 FTSMC020_TPR_AT2(1)	|	\
					 FTSMC020_TPR_WTC(1)	|	\
					 FTSMC020_TPR_AHT(1)	|	\
					 FTSMC020_TPR_TRNA(1))
#endif

/*
 * FLASH on ADP_AG101P is connected to BANK0
 * Just disalbe the other BANK to avoid detection error.
 */
#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
				 FTSMC020_BANK_SIZE_32M           |	\
				 FTSMC020_BANK_MBW_32)

#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_AST(3)   |	\
				 FTSMC020_TPR_CTW(3)   |	\
				 FTSMC020_TPR_ATI(0xf) |	\
				 FTSMC020_TPR_AT2(3)   |	\
				 FTSMC020_TPR_WTC(3)   |	\
				 FTSMC020_TPR_AHT(3)   |	\
				 FTSMC020_TPR_TRNA(0xf))

#define FTSMC020_BANK1_CONFIG	(0x00)
#define FTSMC020_BANK1_TIMING	(0x00)
#endif /* CONFIG_FTSMC020 */

/*
 * FLASH and environment organization
 */
/* use CFI framework */

#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL

/* support JEDEC */
#ifdef CONFIG_CFI_FLASH
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
#endif

/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
#define PHYS_FLASH_1			0x88000000	/* BANK 0 */
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */

/* max number of memory banks */
/*
 * There are 4 banks supported for this Controller,
 * but we have only 1 bank connected to flash on board
 */
#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#endif
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}

/* max number of sectors on one chip */
#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2)
#define CONFIG_SYS_MAX_FLASH_SECT	512

/* environments */
#define CONFIG_ENV_OVERWRITE


/* SPI FLASH */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 16 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */

/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)
/* Increase max gunzip size */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
b841b6e9	2	/*
	3	* Copyright (C) 2011 Andes Technology Corporation
	4	* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
	5	* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
b841b6e9	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	#include <asm/arch-ae3xx/ae3xx.h>
	12
	13	/*
	14	* CPU and Board Configuration Options
	15	*/
	16	#define CONFIG_USE_INTERRUPT
	17
	18	#define CONFIG_SKIP_LOWLEVEL_INIT
	19
	20	#define CONFIG_SKIP_TRUNOFF_WATCHDOG
	21
e336b73d	22	#define CONFIG_ARCH_MAP_SYSMEM
b841b6e9	23
	24	#define CONFIG_BOOTP_SEND_HOSTNAME
	25	#define CONFIG_BOOTP_SERVERIP
	26
	27	#ifdef CONFIG_SKIP_LOWLEVEL_INIT
b841b6e9	28	#ifdef CONFIG_OF_CONTROL
	29	#undef CONFIG_OF_SEPARATE
	30	#define CONFIG_OF_EMBED
	31	#endif
b841b6e9	32	#endif
	33
	34	/*
	35	* Timer
	36	*/
	37	#define CONFIG_SYS_CLK_FREQ 39062500
	38	#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
	39
	40	/*
	41	* Use Externel CLOCK or PCLK
	42	*/
	43	#undef CONFIG_FTRTC010_EXTCLK
	44
	45	#ifndef CONFIG_FTRTC010_EXTCLK
	46	#define CONFIG_FTRTC010_PCLK
	47	#endif
	48
	49	#ifdef CONFIG_FTRTC010_EXTCLK
	50	#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
	51	#else
	52	#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
	53	#endif
	54
	55	#define TIMER_LOAD_VAL 0xffffffff
	56
	57	/*
	58	* Real Time Clock
	59	*/
	60	#define CONFIG_RTC_FTRTC010
	61
	62	/*
	63	* Real Time Clock Divider
	64	* RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
	65	*/
	66	#define OSC_5MHZ (5*1000000)
	67	#define OSC_CLK (4*OSC_5MHZ)
	68	#define RTC_DIV_COUNT (0.5) /* Why?? */
	69
	70	/*
	71	* Serial console configuration
	72	*/
	73
	74	/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
b841b6e9	75	#define CONFIG_SYS_NS16550_SERIAL
	76	#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
	77	#ifndef CONFIG_DM_SERIAL
	78	#define CONFIG_SYS_NS16550_REG_SIZE -4
	79	#endif
	80	#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
	81
b841b6e9	82	/*
	83	* Miscellaneous configurable options
	84	*/
b841b6e9	85
b841b6e9	86	/*
	87	* Size of malloc() pool
	88	*/
	89	/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
	90	#define CONFIG_SYS_MALLOC_LEN (512 << 10)
	91
	92	/*
	93	* Physical Memory Map
	94	*/
	95	#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
	96
	97	#define PHYS_SDRAM_1 \
	98	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
	99
b841b6e9	100	#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
	101	#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
	102
	103	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
	104
	105	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
	106	GENERATED_GBL_DATA_SIZE)
	107
	108	/*
	109	* Load address and memory test area should agree with
	110	* arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
	111	*/
	112	#define CONFIG_SYS_LOAD_ADDR 0x300000
	113
	114	/* memtest works on 63 MB in DRAM */
b841b6e9	115
	116	/*
	117	* Static memory controller configuration
	118	*/
	119	#define CONFIG_FTSMC020
	120
	121	#ifdef CONFIG_FTSMC020
	122	#include <faraday/ftsmc020.h>
	123
	124	#define CONFIG_SYS_FTSMC020_CONFIGS { \
	125	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
	126	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
	127	}
	128
	129	#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
	130	#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE \| \
	131	FTSMC020_BANK_SIZE_32M \| \
	132	FTSMC020_BANK_MBW_32)
	133
	134	#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE \| \
	135	FTSMC020_TPR_AST(1) \| \
	136	FTSMC020_TPR_CTW(1) \| \
	137	FTSMC020_TPR_ATI(1) \| \
	138	FTSMC020_TPR_AT2(1) \| \
	139	FTSMC020_TPR_WTC(1) \| \
	140	FTSMC020_TPR_AHT(1) \| \
	141	FTSMC020_TPR_TRNA(1))
	142	#endif
	143
	144	/*
	145	* FLASH on ADP_AG101P is connected to BANK0
	146	* Just disalbe the other BANK to avoid detection error.
	147	*/
	148	#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE \| \
	149	FTSMC020_BANK_BASE(PHYS_FLASH_1) \| \
	150	FTSMC020_BANK_SIZE_32M \| \
	151	FTSMC020_BANK_MBW_32)
	152
	153	#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) \| \
	154	FTSMC020_TPR_CTW(3) \| \
	155	FTSMC020_TPR_ATI(0xf) \| \
	156	FTSMC020_TPR_AT2(3) \| \
	157	FTSMC020_TPR_WTC(3) \| \
	158	FTSMC020_TPR_AHT(3) \| \
	159	FTSMC020_TPR_TRNA(0xf))
	160
	161	#define FTSMC020_BANK1_CONFIG (0x00)
	162	#define FTSMC020_BANK1_TIMING (0x00)
	163	#endif /* CONFIG_FTSMC020 */
	164
	165	/*
	166	* FLASH and environment organization
	167	*/
	168	/* use CFI framework */
b841b6e9	169
b841b6e9	170	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
b841b6e9	171	#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
	172
	173	/* support JEDEC */
	174	#ifdef CONFIG_CFI_FLASH
	175	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
	176	#endif
	177
	178	/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
	179	#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
	180	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	181	#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
	182	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
	183
	184	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
	185	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
	186
	187	/* max number of memory banks */
	188	/*
	189	* There are 4 banks supported for this Controller,
	190	* but we have only 1 bank connected to flash on board
	191	*/
	192	#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
	193	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	194	#endif
	195	#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
	196
	197	/* max number of sectors on one chip */
	198	#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
b841b6e9	199	#define CONFIG_SYS_MAX_FLASH_SECT 512
	200
	201	/* environments */
b841b6e9	202	#define CONFIG_ENV_OVERWRITE
b841b6e9	203
7b1a50b7	204
7b1a50b7	205	/* SPI FLASH */
7b1a50b7	206
b841b6e9	207	/*
	208	* For booting Linux, the board info and command line data
	209	* have to be in the first 16 MB of memory, since this is
	210	* the maximum mapped by the Linux kernel during initialization.
	211	*/
	212
	213	/* Initial Memory map for Linux*/
	214	#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
	215	/* Increase max gunzip size */
	216	#define CONFIG_SYS_BOOTM_LEN (64 << 20)
	217
	218	#endif /* __CONFIG_H */