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915162da S |
1 | /* |
2 | * am3517_crane.h - Default configuration for AM3517 CraneBoard. | |
3 | * | |
4 | * Author: Srinath.R <srinath@mistralsolutions.com> | |
5 | * | |
6 | * Based on include/configs/am3517evm.h | |
7 | * | |
8 | * Copyright (C) 2011 Mistral Solutions pvt Ltd | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
915162da S |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
3709844f AA |
16 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
17 | ||
915162da S |
18 | /* |
19 | * High Level Configuration Options | |
20 | */ | |
915162da | 21 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
915162da | 22 | #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ |
806d2792 | 23 | #define CONFIG_OMAP_COMMON |
c6f90e14 NM |
24 | /* Common ARM Erratas */ |
25 | #define CONFIG_ARM_ERRATA_454179 | |
26 | #define CONFIG_ARM_ERRATA_430973 | |
27 | #define CONFIG_ARM_ERRATA_621766 | |
915162da S |
28 | |
29 | #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ | |
30 | ||
31 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
987ec585 | 32 | #include <asm/arch/omap.h> |
915162da S |
33 | |
34 | /* | |
35 | * Display CPU and Board information | |
36 | */ | |
37 | #define CONFIG_DISPLAY_CPUINFO 1 | |
38 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
39 | ||
40 | /* Clock Defines */ | |
41 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
42 | #define V_SCLK (V_OSCK >> 1) | |
43 | ||
915162da S |
44 | #define CONFIG_MISC_INIT_R |
45 | ||
46 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
47 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
48 | #define CONFIG_INITRD_TAG 1 | |
49 | #define CONFIG_REVISION_TAG 1 | |
50 | ||
51 | /* | |
52 | * Size of malloc() pool | |
53 | */ | |
54 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ | |
55 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) | |
56 | /* initial data */ | |
57 | /* | |
58 | * DDR related | |
59 | */ | |
915162da S |
60 | #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) |
61 | ||
62 | /* | |
63 | * Hardware drivers | |
64 | */ | |
65 | ||
66 | /* | |
67 | * NS16550 Configuration | |
68 | */ | |
69 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
70 | ||
915162da S |
71 | #define CONFIG_SYS_NS16550_SERIAL |
72 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
73 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
74 | ||
75 | /* | |
76 | * select serial console configuration | |
77 | */ | |
78 | #define CONFIG_CONS_INDEX 3 | |
79 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
80 | #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ | |
81 | ||
82 | /* allow to overwrite serial and ethaddr */ | |
83 | #define CONFIG_ENV_OVERWRITE | |
84 | #define CONFIG_BAUDRATE 115200 | |
85 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
86 | 115200} | |
a5a8821c | 87 | #define CONFIG_GENERIC_MMC 1 |
915162da | 88 | #define CONFIG_MMC 1 |
a5a8821c | 89 | #define CONFIG_OMAP_HSMMC 1 |
915162da S |
90 | #define CONFIG_DOS_PARTITION 1 |
91 | ||
92 | /* | |
93 | * USB configuration | |
95de1e2f PK |
94 | * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard |
95 | * Enable CONFIG_USB_MUSB_UDC for Device functionalities. | |
915162da S |
96 | */ |
97 | #define CONFIG_USB_AM35X 1 | |
95de1e2f | 98 | #define CONFIG_USB_MUSB_HCD 1 |
915162da S |
99 | |
100 | #ifdef CONFIG_USB_AM35X | |
101 | ||
95de1e2f | 102 | #ifdef CONFIG_USB_MUSB_HCD |
915162da S |
103 | |
104 | #define CONFIG_USB_STORAGE | |
105 | #define CONGIG_CMD_STORAGE | |
915162da S |
106 | |
107 | #ifdef CONFIG_USB_KEYBOARD | |
108 | #define CONFIG_SYS_USB_EVENT_POLL | |
109 | #define CONFIG_PREBOOT "usb start" | |
110 | #endif /* CONFIG_USB_KEYBOARD */ | |
111 | ||
95de1e2f | 112 | #endif /* CONFIG_USB_MUSB_HCD */ |
915162da | 113 | |
95de1e2f | 114 | #ifdef CONFIG_USB_MUSB_UDC |
915162da S |
115 | /* USB device configuration */ |
116 | #define CONFIG_USB_DEVICE 1 | |
117 | #define CONFIG_USB_TTY 1 | |
118 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 | |
119 | /* Change these to suit your needs */ | |
120 | #define CONFIG_USBD_VENDORID 0x0451 | |
121 | #define CONFIG_USBD_PRODUCTID 0x5678 | |
122 | #define CONFIG_USBD_MANUFACTURER "Texas Instruments" | |
123 | #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" | |
95de1e2f | 124 | #endif /* CONFIG_USB_MUSB_UDC */ |
915162da S |
125 | |
126 | #endif /* CONFIG_USB_AM35X */ | |
127 | ||
128 | /* commands to include */ | |
915162da S |
129 | #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ |
130 | ||
915162da | 131 | #define CONFIG_CMD_NAND /* NAND support */ |
915162da | 132 | |
915162da | 133 | #define CONFIG_SYS_NO_FLASH |
6789e84e HS |
134 | #define CONFIG_SYS_I2C |
135 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 | |
136 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
137 | #define CONFIG_SYS_I2C_OMAP34XX | |
915162da | 138 | |
915162da S |
139 | /* |
140 | * Board NAND Info. | |
141 | */ | |
142 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
143 | /* to access nand */ | |
144 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
145 | /* to access */ | |
146 | /* nand at CS0 */ | |
147 | ||
148 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ | |
149 | /* NAND devices */ | |
915162da S |
150 | |
151 | #define CONFIG_JFFS2_NAND | |
152 | /* nand device jffs2 lives on */ | |
153 | #define CONFIG_JFFS2_DEV "nand0" | |
154 | /* start of jffs2 partition */ | |
155 | #define CONFIG_JFFS2_PART_OFFSET 0x680000 | |
156 | #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ | |
157 | ||
158 | /* Environment information */ | |
915162da | 159 | |
b3f44c21 | 160 | #define CONFIG_BOOTFILE "uImage" |
915162da S |
161 | |
162 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
163 | "loadaddr=0x82000000\0" \ | |
164 | "console=ttyS2,115200n8\0" \ | |
a5a8821c | 165 | "mmcdev=0\0" \ |
915162da S |
166 | "mmcargs=setenv bootargs console=${console} " \ |
167 | "root=/dev/mmcblk0p2 rw " \ | |
168 | "rootfstype=ext3 rootwait\0" \ | |
169 | "nandargs=setenv bootargs console=${console} " \ | |
170 | "root=/dev/mtdblock4 rw " \ | |
171 | "rootfstype=jffs2\0" \ | |
a5a8821c | 172 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
915162da S |
173 | "bootscript=echo Running bootscript from mmc ...; " \ |
174 | "source ${loadaddr}\0" \ | |
a5a8821c | 175 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
915162da S |
176 | "mmcboot=echo Booting from mmc ...; " \ |
177 | "run mmcargs; " \ | |
178 | "bootm ${loadaddr}\0" \ | |
179 | "nandboot=echo Booting from nand ...; " \ | |
180 | "run nandargs; " \ | |
181 | "nand read ${loadaddr} 280000 400000; " \ | |
182 | "bootm ${loadaddr}\0" \ | |
183 | ||
184 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 185 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
915162da S |
186 | "if run loadbootscript; then " \ |
187 | "run bootscript; " \ | |
188 | "else " \ | |
189 | "if run loaduimage; then " \ | |
190 | "run mmcboot; " \ | |
191 | "else run nandboot; " \ | |
192 | "fi; " \ | |
193 | "fi; " \ | |
194 | "else run nandboot; fi" | |
195 | ||
196 | #define CONFIG_AUTO_COMPLETE 1 | |
197 | /* | |
198 | * Miscellaneous configurable options | |
199 | */ | |
915162da | 200 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
915162da S |
201 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
202 | /* Print Buffer Size */ | |
203 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
204 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
205 | #define CONFIG_SYS_MAXARGS 32 /* max number of command */ | |
206 | /* args */ | |
207 | /* Boot Argument Buffer Size */ | |
208 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
209 | /* memtest works on */ | |
210 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) | |
211 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
212 | 0x01F00000) /* 31MB */ | |
213 | ||
214 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ | |
215 | /* address */ | |
216 | ||
217 | /* | |
218 | * AM3517 has 12 GP timers, they can be driven by the system clock | |
219 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
220 | * This rate is divided by a local divisor. | |
221 | */ | |
222 | #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 | |
223 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
915162da | 224 | |
915162da S |
225 | /*----------------------------------------------------------------------- |
226 | * Physical Memory Map | |
227 | */ | |
228 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
229 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
915162da S |
230 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
231 | ||
915162da S |
232 | /*----------------------------------------------------------------------- |
233 | * FLASH and environment organization | |
234 | */ | |
235 | ||
236 | /* **** PISMO SUPPORT *** */ | |
915162da S |
237 | #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ |
238 | /* on one chip */ | |
239 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ | |
240 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ | |
241 | ||
222a3113 | 242 | #define CONFIG_SYS_FLASH_BASE NAND_BASE |
915162da S |
243 | |
244 | /* Monitor at start of flash */ | |
245 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
246 | ||
247 | #define CONFIG_NAND_OMAP_GPMC | |
915162da S |
248 | #define CONFIG_ENV_IS_IN_NAND 1 |
249 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
250 | ||
6cbec7b3 LC |
251 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ |
252 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
253 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET | |
915162da S |
254 | |
255 | /*----------------------------------------------------------------------- | |
256 | * CFI FLASH driver setup | |
257 | */ | |
258 | /* timeout values are in ticks */ | |
259 | #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) | |
260 | #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) | |
261 | ||
262 | /* Flash banks JFFS2 should use */ | |
263 | #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ | |
264 | CONFIG_SYS_MAX_NAND_DEVICE) | |
265 | #define CONFIG_SYS_JFFS2_MEM_NAND | |
266 | /* use flash_info[2] */ | |
267 | #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS | |
268 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
269 | ||
915162da S |
270 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
271 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
272 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
273 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
274 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
275 | GENERATED_GBL_DATA_SIZE) | |
d067cc46 TR |
276 | |
277 | /* Defines for SPL */ | |
47f7bcae | 278 | #define CONFIG_SPL_FRAMEWORK |
d7cb93b2 | 279 | #define CONFIG_SPL_BOARD_INIT |
d067cc46 TR |
280 | #define CONFIG_SPL_NAND_SIMPLE |
281 | #define CONFIG_SPL_TEXT_BASE 0x40200800 | |
e0820ccc | 282 | #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ |
d067cc46 TR |
283 | |
284 | #define CONFIG_SPL_BSS_START_ADDR 0x80000000 | |
285 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ | |
286 | ||
287 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ | |
288 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ | |
e2ccdf89 | 289 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
205b4f33 | 290 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
d067cc46 TR |
291 | |
292 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
293 | #define CONFIG_SPL_LIBDISK_SUPPORT | |
294 | #define CONFIG_SPL_I2C_SUPPORT | |
295 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
296 | #define CONFIG_SPL_MMC_SUPPORT | |
297 | #define CONFIG_SPL_FAT_SUPPORT | |
298 | #define CONFIG_SPL_SERIAL_SUPPORT | |
299 | #define CONFIG_SPL_NAND_SUPPORT | |
6f2f01b9 SW |
300 | #define CONFIG_SPL_NAND_BASE |
301 | #define CONFIG_SPL_NAND_DRIVERS | |
302 | #define CONFIG_SPL_NAND_ECC | |
d067cc46 TR |
303 | #define CONFIG_SPL_POWER_SUPPORT |
304 | #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" | |
305 | ||
306 | /* NAND boot config */ | |
55f1b39f | 307 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT |
d067cc46 TR |
308 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
309 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
310 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
311 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
312 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
313 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
314 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ | |
315 | 10, 11, 12, 13} | |
316 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
317 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
3f719069 | 318 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW |
d067cc46 TR |
319 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
320 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
321 | ||
322 | /* | |
323 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM | |
324 | * 64 bytes before this address should be set aside for u-boot.img's | |
325 | * header. That is 0x800FFFC0--0x80100000 should not be used for any | |
326 | * other needs. | |
327 | */ | |
328 | #define CONFIG_SYS_TEXT_BASE 0x80100000 | |
329 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
330 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
331 | ||
915162da | 332 | #endif /* __CONFIG_H */ |