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Commit | Line | Data |
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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
06fd66a4 | 2 | /* |
3 | * Sysam AMCORE board configuration | |
4 | * | |
9deff607 | 5 | * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it> |
06fd66a4 | 6 | */ |
7 | ||
8 | #ifndef __AMCORE_CONFIG_H | |
9 | #define __AMCORE_CONFIG_H | |
10 | ||
65cc0e2a | 11 | #define CFG_SYS_UART_PORT 0 |
06fd66a4 | 12 | |
9deff607 AD |
13 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
14 | "upgrade_uboot=loady; " \ | |
15 | "protect off 0xffc00000 0xffc1ffff; " \ | |
16 | "erase 0xffc00000 0xffc1ffff; " \ | |
17 | "cp.b 0x20000 0xffc00000 ${filesize}\0" \ | |
18 | "upgrade_kernel=loady; " \ | |
19 | "erase 0xffc20000 0xffefffff; " \ | |
20 | "cp.b 0x20000 0xffc20000 ${filesize}\0" \ | |
21 | "upgrade_jffs2=loady; " \ | |
22 | "erase 0xfff00000 0xffffffff; " \ | |
23 | "cp.b 0x20000 0xfff00000 ${filesize}\0" | |
06fd66a4 | 24 | |
65cc0e2a TR |
25 | #define CFG_SYS_CLK 45000000 |
26 | #define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 2) | |
06fd66a4 | 27 | /* Register Base Addrs */ |
65cc0e2a | 28 | #define CFG_SYS_MBAR 0x10000000 |
06fd66a4 | 29 | /* Definitions for initial stack pointer and data area (in DPRAM) */ |
65cc0e2a | 30 | #define CFG_SYS_INIT_RAM_ADDR 0x20000000 |
06fd66a4 | 31 | /* size of internal SRAM */ |
65cc0e2a | 32 | #define CFG_SYS_INIT_RAM_SIZE 0x1000 |
06fd66a4 | 33 | |
aa6e94de TR |
34 | #define CFG_SYS_SDRAM_BASE 0x00000000 |
35 | #define CFG_SYS_SDRAM_SIZE 0x1000000 | |
65cc0e2a | 36 | #define CFG_SYS_FLASH_BASE 0xffc00000 |
06fd66a4 | 37 | |
06fd66a4 | 38 | /* amcore design has flash data bytes wired swapped */ |
65cc0e2a | 39 | #define CFG_SYS_WRITE_SWAPPED_DATA |
06fd66a4 | 40 | /* reserve 128-4KB */ |
06fd66a4 | 41 | |
5296cb1d | 42 | #define LDS_BOARD_TEXT \ |
0649cd0d SG |
43 | . = DEFINED(env_offset) ? env_offset : .; \ |
44 | env/embedded.o(.text*); | |
5296cb1d | 45 | |
06fd66a4 | 46 | /* memory map space for linux boot data */ |
65cc0e2a | 47 | #define CFG_SYS_BOOTMAPSZ (8 << 20) |
06fd66a4 | 48 | |
49 | /* | |
50 | * Cache Configuration | |
51 | * | |
52 | * Special 8K version 3 core cache. | |
53 | * This is a single unified instruction/data cache. | |
54 | * sdram - single region - no masks | |
55 | */ | |
06fd66a4 | 56 | |
65cc0e2a TR |
57 | #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
58 | CFG_SYS_INIT_RAM_SIZE - 8) | |
59 | #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ | |
60 | CFG_SYS_INIT_RAM_SIZE - 4) | |
61 | #define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) | |
62 | #define CFG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ | |
06fd66a4 | 63 | CF_ACR_EN) |
65cc0e2a | 64 | #define CFG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ |
06fd66a4 | 65 | CF_CACR_EC) |
66 | ||
67 | /* CS0 - AMD Flash, address 0xffc00000 */ | |
65cc0e2a | 68 | #define CFG_SYS_CS0_BASE (CFG_SYS_FLASH_BASE>>16) |
06fd66a4 | 69 | /* 4MB, AA=0,V=1 C/I BIT for errata */ |
65cc0e2a | 70 | #define CFG_SYS_CS0_MASK 0x003f0001 |
06fd66a4 | 71 | /* WS=10, AA=1, PS=16bit (10) */ |
65cc0e2a | 72 | #define CFG_SYS_CS0_CTRL 0x1980 |
06fd66a4 | 73 | /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ |
65cc0e2a TR |
74 | #define CFG_SYS_CS1_BASE 0x3000 |
75 | #define CFG_SYS_CS1_MASK 0x00070001 | |
76 | #define CFG_SYS_CS1_CTRL 0x0100 | |
06fd66a4 | 77 | |
78 | #endif /* __AMCORE_CONFIG_H */ |