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6f0da497 NI |
1 | /* |
2 | * Configuation settings for the Renesas Solutions AP-325RXA board | |
3 | * | |
4 | * Copyright (C) 2008 Renesas Solutions Corp. | |
5 | * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
6f0da497 NI |
8 | */ |
9 | ||
10 | #ifndef __AP325RXA_H | |
11 | #define __AP325RXA_H | |
12 | ||
13 | #undef DEBUG | |
6f0da497 NI |
14 | #define CONFIG_CPU_SH7723 1 |
15 | #define CONFIG_AP325RXA 1 | |
16 | ||
6f0da497 | 17 | #define CONFIG_CMD_PING |
6f0da497 | 18 | #define CONFIG_CMD_SDRAM |
6f0da497 NI |
19 | #define CONFIG_CMD_IDE |
20 | #define CONFIG_CMD_EXT2 | |
21 | #define CONFIG_DOS_PARTITION | |
22 | ||
23 | #define CONFIG_BAUDRATE 38400 | |
24 | #define CONFIG_BOOTDELAY 3 | |
25 | #define CONFIG_BOOTARGS "console=ttySC2,38400" | |
26 | ||
27 | #define CONFIG_VERSION_VARIABLE | |
28 | #undef CONFIG_SHOW_BOOT_PROGRESS | |
29 | ||
30 | /* SMC9118 */ | |
736fead8 BW |
31 | #define CONFIG_SMC911X 1 |
32 | #define CONFIG_SMC911X_32_BIT 1 | |
33 | #define CONFIG_SMC911X_BASE 0xB6080000 | |
6f0da497 NI |
34 | |
35 | /* MEMORY */ | |
36 | #define AP325RXA_SDRAM_BASE (0x88000000) | |
37 | #define AP325RXA_FLASH_BASE_1 (0xA0000000) | |
38 | #define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024) | |
39 | ||
db68b703 NI |
40 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 |
41 | ||
6f0da497 | 42 | /* undef to save memory */ |
6d0f6bcf | 43 | #define CONFIG_SYS_LONGHELP |
6f0da497 | 44 | /* Monitor Command Prompt */ |
6f0da497 | 45 | /* Buffer size for input from the Console */ |
6d0f6bcf | 46 | #define CONFIG_SYS_CBSIZE 256 |
6f0da497 | 47 | /* Buffer size for Console output */ |
6d0f6bcf | 48 | #define CONFIG_SYS_PBSIZE 256 |
6f0da497 | 49 | /* max args accepted for monitor commands */ |
6d0f6bcf | 50 | #define CONFIG_SYS_MAXARGS 16 |
6f0da497 | 51 | /* Buffer size for Boot Arguments passed to kernel */ |
6d0f6bcf | 52 | #define CONFIG_SYS_BARGSIZE 512 |
6f0da497 | 53 | /* List of legal baudrate settings for this board */ |
6d0f6bcf | 54 | #define CONFIG_SYS_BAUDRATE_TABLE { 38400 } |
6f0da497 NI |
55 | |
56 | /* SCIF */ | |
57 | #define CONFIG_SCIF_CONSOLE 1 | |
58 | #define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */ | |
59 | #define CONFIG_CONS_SCIF5 1 | |
60 | ||
61 | /* Suppress display of console information at boot */ | |
6d0f6bcf JCPV |
62 | #undef CONFIG_SYS_CONSOLE_INFO_QUIET |
63 | #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
64 | #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE | |
6f0da497 | 65 | |
6d0f6bcf JCPV |
66 | #define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE) |
67 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) | |
6f0da497 NI |
68 | |
69 | /* Enable alternate, more extensive, memory test */ | |
6d0f6bcf | 70 | #undef CONFIG_SYS_ALT_MEMTEST |
6f0da497 | 71 | /* Scratch address used by the alternate memory test */ |
6d0f6bcf | 72 | #undef CONFIG_SYS_MEMTEST_SCRATCH |
6f0da497 NI |
73 | |
74 | /* Enable temporary baudrate change while serial download */ | |
6d0f6bcf | 75 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
6f0da497 | 76 | |
6d0f6bcf | 77 | #define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE) |
6f0da497 | 78 | /* maybe more, but if so u-boot doesn't know about it... */ |
6d0f6bcf | 79 | #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) |
6f0da497 | 80 | /* default load address for scripts ?!? */ |
6d0f6bcf | 81 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) |
6f0da497 NI |
82 | |
83 | /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ | |
6d0f6bcf | 84 | #define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1) |
6f0da497 | 85 | /* Monitor size */ |
6d0f6bcf | 86 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) |
6f0da497 | 87 | /* Size of DRAM reserved for malloc() use */ |
6d0f6bcf | 88 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
6d0f6bcf | 89 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
6f0da497 NI |
90 | |
91 | /* FLASH */ | |
92 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_FLASH_CFI |
94 | #undef CONFIG_SYS_FLASH_QUIET_TEST | |
6f0da497 | 95 | /* print 'E' for empty sector on flinfo */ |
6d0f6bcf | 96 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
6f0da497 | 97 | /* Physical start address of Flash memory */ |
6d0f6bcf | 98 | #define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1) |
6f0da497 | 99 | /* Max number of sectors on each Flash chip */ |
6d0f6bcf | 100 | #define CONFIG_SYS_MAX_FLASH_SECT 512 |
6f0da497 NI |
101 | |
102 | /* | |
103 | * IDE support | |
104 | */ | |
105 | #define CONFIG_IDE_RESET 1 | |
6d0f6bcf JCPV |
106 | #define CONFIG_SYS_PIO_MODE 1 |
107 | #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ | |
108 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
109 | #define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000 | |
110 | #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ | |
111 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */ | |
112 | #define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */ | |
113 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */ | |
f2a37fcd | 114 | #define CONFIG_IDE_SWAP_IO |
6f0da497 NI |
115 | |
116 | /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ | |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
118 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)} | |
6f0da497 NI |
119 | |
120 | /* Timeout for Flash erase operations (in ms) */ | |
6d0f6bcf | 121 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
6f0da497 | 122 | /* Timeout for Flash write operations (in ms) */ |
6d0f6bcf | 123 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) |
6f0da497 | 124 | /* Timeout for Flash set sector lock bit operations (in ms) */ |
6d0f6bcf | 125 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) |
6f0da497 | 126 | /* Timeout for Flash clear lock bit operations (in ms) */ |
6d0f6bcf | 127 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) |
6f0da497 NI |
128 | |
129 | /* | |
130 | * Use hardware flash sectors protection instead | |
131 | * of U-Boot software protection | |
132 | */ | |
6d0f6bcf JCPV |
133 | #undef CONFIG_SYS_FLASH_PROTECTION |
134 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP | |
6f0da497 NI |
135 | |
136 | /* ENV setting */ | |
5a1aceb0 | 137 | #define CONFIG_ENV_IS_IN_FLASH |
6f0da497 | 138 | #define CONFIG_ENV_OVERWRITE 1 |
0e8d1586 JCPV |
139 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
140 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
141 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
142 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ | |
143 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) | |
0e8d1586 | 144 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
6f0da497 NI |
145 | |
146 | /* Board Clock */ | |
147 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
684a501e NI |
148 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
149 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 150 | #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ |
6f0da497 NI |
151 | |
152 | #endif /* __AP325RXA_H */ |