[thirdparty/u-boot.git] / include / configs / ap325rxa.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Configuation settings for the Renesas Solutions AP-325RXA board
 *
 * Copyright (C) 2008 Renesas Solutions Corp.
 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
 */

#ifndef __AP325RXA_H
#define __AP325RXA_H

#define CONFIG_CPU_SH7723	1

#define CONFIG_DISPLAY_BOARDINFO
#undef  CONFIG_SHOW_BOOT_PROGRESS

/* MEMORY */
#define AP325RXA_SDRAM_BASE		(0x88000000)
#define AP325RXA_FLASH_BASE_1		(0xA0000000)
#define AP325RXA_FLASH_BANK_SIZE	(128 * 1024 * 1024)

/* undef to save memory	*/
/* Monitor Command Prompt */
/* Buffer size for Console output */
#define CONFIG_SYS_PBSIZE		256
/* List of legal baudrate settings for this board */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400 }

/* SCIF */
#define CONFIG_SCIF_A		1 /* SH7723 has SCIF and SCIFA */
#define CONFIG_CONS_SCIF5	1

/* Suppress display of console information at boot */

#define CONFIG_SYS_MEMTEST_START	(AP325RXA_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))

/* Enable alternate, more extensive, memory test */
/* Scratch address used by the alternate memory test */
#undef  CONFIG_SYS_MEMTEST_SCRATCH

/* Enable temporary baudrate change while serial download */
#undef  CONFIG_SYS_LOADS_BAUD_CHANGE

#define CONFIG_SYS_SDRAM_BASE	(AP325RXA_SDRAM_BASE)
/* maybe more, but if so u-boot doesn't know about it... */
#define CONFIG_SYS_SDRAM_SIZE	(128 * 1024 * 1024)
/* default load address for scripts ?!? */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)

/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
#define CONFIG_SYS_MONITOR_BASE	(AP325RXA_FLASH_BASE_1)
/* Monitor size */
#define CONFIG_SYS_MONITOR_LEN	(128 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)

/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI
#undef  CONFIG_SYS_FLASH_QUIET_TEST
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Physical start address of Flash memory */
#define CONFIG_SYS_FLASH_BASE	(AP325RXA_FLASH_BASE_1)
/* Max number of sectors on each Flash chip */
#define CONFIG_SYS_MAX_FLASH_SECT	512

/*
 * IDE support
 */
#define CONFIG_IDE_RESET	1
#define CONFIG_SYS_PIO_MODE		1
#define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE	1
#define CONFIG_SYS_ATA_BASE_ADDR	0xB4180000
#define CONFIG_SYS_ATA_STRIDE		2	/* 1bit shift */
#define CONFIG_SYS_ATA_DATA_OFFSET	0x200	/* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET	0x200	/* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x210	/* alternate register offset */
#define CONFIG_IDE_SWAP_IO

/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}

/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)

/*
 * Use hardware flash sectors protection instead
 * of U-Boot software protection
 */
#undef  CONFIG_SYS_FLASH_PROTECTION
#undef  CONFIG_SYS_DIRECT_FLASH_TFTP

/* ENV setting */
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */

#endif	/* __AP325RXA_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
6f0da497 NI	2	/*
	3	* Configuation settings for the Renesas Solutions AP-325RXA board
	4	*
	5	* Copyright (C) 2008 Renesas Solutions Corp.
	6	* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
6f0da497 NI	7	*/
	8
	9	#ifndef __AP325RXA_H
	10	#define __AP325RXA_H
	11
6f0da497	12	#define CONFIG_CPU_SH7723 1
6f0da497	13
18a40e84	14	#define CONFIG_DISPLAY_BOARDINFO
6f0da497 NI	15	#undef CONFIG_SHOW_BOOT_PROGRESS
6f0da497 NI	16
6f0da497 NI	17	/* MEMORY */
	18	#define AP325RXA_SDRAM_BASE (0x88000000)
	19	#define AP325RXA_FLASH_BASE_1 (0xA0000000)
	20	#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
	21
	22	/* undef to save memory */
6f0da497	23	/* Monitor Command Prompt */
6f0da497	24	/* Buffer size for Console output */
6d0f6bcf	25	#define CONFIG_SYS_PBSIZE 256
6f0da497	26	/* List of legal baudrate settings for this board */
6d0f6bcf	27	#define CONFIG_SYS_BAUDRATE_TABLE { 38400 }
6f0da497 NI	28
6f0da497 NI	29	/* SCIF */
6f0da497 NI	30	#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
	31	#define CONFIG_CONS_SCIF5 1
	32
	33	/* Suppress display of console information at boot */
6f0da497	34
6d0f6bcf JCPV	35	#define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE)
6d0f6bcf JCPV	36	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
6f0da497 NI	37
6f0da497 NI	38	/* Enable alternate, more extensive, memory test */
6f0da497	39	/* Scratch address used by the alternate memory test */
6d0f6bcf	40	#undef CONFIG_SYS_MEMTEST_SCRATCH
6f0da497 NI	41
6f0da497 NI	42	/* Enable temporary baudrate change while serial download */
6d0f6bcf	43	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
6f0da497	44
6d0f6bcf	45	#define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE)
6f0da497	46	/* maybe more, but if so u-boot doesn't know about it... */
6d0f6bcf	47	#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
6f0da497	48	/* default load address for scripts ?!? */
6d0f6bcf	49	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
6f0da497 NI	50
6f0da497 NI	51	/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
6d0f6bcf	52	#define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1)
6f0da497	53	/* Monitor size */
6d0f6bcf	54	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
6f0da497	55	/* Size of DRAM reserved for malloc() use */
6d0f6bcf	56	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
6d0f6bcf	57	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
6f0da497 NI	58
	59	/* FLASH */
	60	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	61	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	62	#undef CONFIG_SYS_FLASH_QUIET_TEST
6f0da497	63	/* print 'E' for empty sector on flinfo */
6d0f6bcf	64	#define CONFIG_SYS_FLASH_EMPTY_INFO
6f0da497	65	/* Physical start address of Flash memory */
6d0f6bcf	66	#define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1)
6f0da497	67	/* Max number of sectors on each Flash chip */
6d0f6bcf	68	#define CONFIG_SYS_MAX_FLASH_SECT 512
6f0da497 NI	69
	70	/*
	71	* IDE support
	72	*/
	73	#define CONFIG_IDE_RESET 1
6d0f6bcf JCPV	74	#define CONFIG_SYS_PIO_MODE 1
	75	#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
	76	#define CONFIG_SYS_IDE_MAXDEVICE 1
	77	#define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000
	78	#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
	79	#define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */
	80	#define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */
	81	#define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */
f2a37fcd	82	#define CONFIG_IDE_SWAP_IO
6f0da497 NI	83
6f0da497 NI	84	/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
6d0f6bcf JCPV	85	#define CONFIG_SYS_MAX_FLASH_BANKS 1
6d0f6bcf JCPV	86	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
6f0da497 NI	87
6f0da497 NI	88	/* Timeout for Flash erase operations (in ms) */
6d0f6bcf	89	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
6f0da497	90	/* Timeout for Flash write operations (in ms) */
6d0f6bcf	91	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
6f0da497	92	/* Timeout for Flash set sector lock bit operations (in ms) */
6d0f6bcf	93	#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
6f0da497	94	/* Timeout for Flash clear lock bit operations (in ms) */
6d0f6bcf	95	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
6f0da497 NI	96
	97	/*
	98	* Use hardware flash sectors protection instead
	99	* of U-Boot software protection
	100	*/
6d0f6bcf JCPV	101	#undef CONFIG_SYS_FLASH_PROTECTION
6d0f6bcf JCPV	102	#undef CONFIG_SYS_DIRECT_FLASH_TFTP
6f0da497 NI	103
6f0da497 NI	104	/* ENV setting */
6f0da497	105	#define CONFIG_ENV_OVERWRITE 1
0e8d1586 JCPV	106	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
0e8d1586 JCPV	107	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf JCPV	108	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
	109	/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
	110	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
0e8d1586	111	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
6f0da497 NI	112
	113	/* Board Clock */
	114	#define CONFIG_SYS_CLK_FREQ 33333333
684a501e NI	115	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	116	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	117	#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
6f0da497 NI	118
6f0da497 NI	119	#endif /* __AP325RXA_H */