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bfc93fb4 NI |
1 | /* |
2 | * Configuation settings for the Alpha Project AP-SH4A-4A board | |
3 | * | |
4 | * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
bfc93fb4 NI |
7 | */ |
8 | ||
9 | #ifndef __AP_SH4A_4A_H | |
10 | #define __AP_SH4A_4A_H | |
11 | ||
12 | #undef DEBUG | |
bfc93fb4 NI |
13 | #define CONFIG_CPU_SH7734 1 |
14 | #define CONFIG_AP_SH4A_4A 1 | |
15 | #define CONFIG_400MHZ_MODE 1 | |
16 | /* #define CONFIG_533MHZ_MODE 1 */ | |
17 | ||
18 | #define CONFIG_BOARD_LATE_INIT | |
19 | #define CONFIG_SYS_TEXT_BASE 0x8BFC0000 | |
20 | ||
bfc93fb4 NI |
21 | #define CONFIG_CMD_SDRAM |
22 | #define CONFIG_CMD_ENV | |
bfc93fb4 NI |
23 | |
24 | #define CONFIG_BAUDRATE 115200 | |
bfc93fb4 NI |
25 | #define CONFIG_BOOTARGS "console=ttySC4,115200" |
26 | ||
bfc93fb4 NI |
27 | #undef CONFIG_SHOW_BOOT_PROGRESS |
28 | ||
29 | /* Ether */ | |
30 | #define CONFIG_SH_ETHER 1 | |
31 | #define CONFIG_SH_ETHER_USE_PORT (0) | |
32 | #define CONFIG_SH_ETHER_PHY_ADDR (0x0) | |
33 | #define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII) | |
34 | #define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */ | |
35 | #define CONFIG_PHYLIB | |
36 | #define CONFIG_PHY_MICREL 1 | |
37 | #define CONFIG_BITBANGMII | |
38 | #define CONFIG_BITBANGMII_MULTI | |
39 | ||
40 | /* I2C */ | |
bfc93fb4 NI |
41 | #define CONFIG_SH_SH7734_I2C 1 |
42 | #define CONFIG_HARD_I2C 1 | |
43 | #define CONFIG_I2C_MULTI_BUS 1 | |
44 | #define CONFIG_SYS_MAX_I2C_BUS 2 | |
45 | #define CONFIG_SYS_I2C_MODULE 0 | |
46 | #define CONFIG_SYS_I2C_SPEED 400000 /* 400 kHz */ | |
47 | #define CONFIG_SYS_I2C_SLAVE 0x50 | |
48 | #define CONFIG_SH_I2C_DATA_HIGH 4 | |
49 | #define CONFIG_SH_I2C_DATA_LOW 5 | |
50 | #define CONFIG_SH_I2C_CLOCK 500000000 | |
51 | #define CONFIG_SH_I2C_BASE0 0xFFC70000 | |
52 | #define CONFIG_SH_I2C_BASE1 0xFFC71000 | |
53 | ||
54 | /* undef to save memory */ | |
55 | #define CONFIG_SYS_LONGHELP | |
56 | /* Monitor Command Prompt */ | |
bfc93fb4 NI |
57 | /* Buffer size for input from the Console */ |
58 | #define CONFIG_SYS_CBSIZE 256 | |
59 | /* Buffer size for Console output */ | |
60 | #define CONFIG_SYS_PBSIZE 256 | |
61 | /* max args accepted for monitor commands */ | |
62 | #define CONFIG_SYS_MAXARGS 16 | |
63 | /* Buffer size for Boot Arguments passed to kernel */ | |
64 | #define CONFIG_SYS_BARGSIZE 512 | |
65 | /* List of legal baudrate settings for this board */ | |
66 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } | |
67 | ||
68 | /* SCIF */ | |
69 | #define CONFIG_SCIF_CONSOLE 1 | |
70 | #define CONFIG_SCIF 1 | |
71 | #define CONFIG_CONS_SCIF4 1 | |
72 | ||
73 | /* Suppress display of console information at boot */ | |
74 | #undef CONFIG_SYS_CONSOLE_INFO_QUIET | |
75 | #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
76 | #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE | |
77 | ||
78 | /* SDRAM */ | |
79 | #define CONFIG_SYS_SDRAM_BASE (0x88000000) | |
80 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) | |
81 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) | |
82 | ||
83 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) | |
84 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE) | |
85 | /* Enable alternate, more extensive, memory test */ | |
86 | #undef CONFIG_SYS_ALT_MEMTEST | |
87 | /* Scratch address used by the alternate memory test */ | |
88 | #undef CONFIG_SYS_MEMTEST_SCRATCH | |
89 | ||
90 | /* Enable temporary baudrate change while serial download */ | |
91 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE | |
92 | ||
93 | /* FLASH */ | |
94 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
95 | #define CONFIG_SYS_FLASH_CFI | |
96 | #undef CONFIG_SYS_FLASH_QUIET_TEST | |
97 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
98 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) | |
99 | #define CONFIG_SYS_MAX_FLASH_SECT 512 | |
100 | ||
101 | /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ | |
102 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
103 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
104 | ||
105 | /* Timeout for Flash erase operations (in ms) */ | |
106 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) | |
107 | /* Timeout for Flash write operations (in ms) */ | |
108 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) | |
109 | /* Timeout for Flash set sector lock bit operations (in ms) */ | |
110 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) | |
111 | /* Timeout for Flash clear lock bit operations (in ms) */ | |
112 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) | |
113 | ||
114 | /* | |
115 | * Use hardware flash sectors protection instead | |
116 | * of U-Boot software protection | |
117 | */ | |
118 | #undef CONFIG_SYS_FLASH_PROTECTION | |
119 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP | |
120 | ||
121 | /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ | |
122 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) | |
123 | /* Monitor size */ | |
124 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
125 | /* Size of DRAM reserved for malloc() use */ | |
126 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) | |
bfc93fb4 NI |
127 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
128 | ||
129 | /* ENV setting */ | |
130 | #define CONFIG_ENV_IS_IN_FLASH | |
131 | #define CONFIG_ENV_OVERWRITE 1 | |
132 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) | |
133 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
134 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) | |
135 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ | |
136 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) | |
137 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) | |
138 | ||
139 | /* Board Clock */ | |
140 | #if defined(CONFIG_400MHZ_MODE) | |
141 | #define CONFIG_SYS_CLK_FREQ 50000000 | |
142 | #else | |
143 | #define CONFIG_SYS_CLK_FREQ 44444444 | |
144 | #endif | |
684a501e NI |
145 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
146 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
bfc93fb4 | 147 | #define CONFIG_SYS_TMU_CLK_DIV 4 |
bfc93fb4 NI |
148 | |
149 | #endif /* __AP_SH4A_4A_H */ |