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1 | /* |
2 | * Configuation settings for the Alpha Project AP-SH4A-4A board | |
3 | * | |
4 | * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | */ | |
20 | ||
21 | #ifndef __AP_SH4A_4A_H | |
22 | #define __AP_SH4A_4A_H | |
23 | ||
24 | #undef DEBUG | |
25 | #define CONFIG_SH 1 | |
26 | #define CONFIG_SH4 1 | |
27 | #define CONFIG_SH4A 1 | |
28 | #define CONFIG_CPU_SH7734 1 | |
29 | #define CONFIG_AP_SH4A_4A 1 | |
30 | #define CONFIG_400MHZ_MODE 1 | |
31 | /* #define CONFIG_533MHZ_MODE 1 */ | |
32 | ||
33 | #define CONFIG_BOARD_LATE_INIT | |
34 | #define CONFIG_SYS_TEXT_BASE 0x8BFC0000 | |
35 | ||
36 | #define CONFIG_CMD_FLASH | |
37 | #define CONFIG_CMD_MEMORY | |
38 | #define CONFIG_CMD_NET | |
39 | #define CONFIG_CMD_PING | |
40 | #define CONFIG_CMD_MII | |
41 | #define CONFIG_CMD_NFS | |
42 | #define CONFIG_CMD_SDRAM | |
43 | #define CONFIG_CMD_ENV | |
44 | #define CONFIG_CMD_SAVEENV | |
45 | ||
46 | #define CONFIG_BAUDRATE 115200 | |
47 | #define CONFIG_BOOTDELAY 3 | |
48 | #define CONFIG_BOOTARGS "console=ttySC4,115200" | |
49 | ||
50 | #define CONFIG_VERSION_VARIABLE | |
51 | #undef CONFIG_SHOW_BOOT_PROGRESS | |
52 | ||
53 | /* Ether */ | |
54 | #define CONFIG_SH_ETHER 1 | |
55 | #define CONFIG_SH_ETHER_USE_PORT (0) | |
56 | #define CONFIG_SH_ETHER_PHY_ADDR (0x0) | |
57 | #define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII) | |
58 | #define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */ | |
59 | #define CONFIG_PHYLIB | |
60 | #define CONFIG_PHY_MICREL 1 | |
61 | #define CONFIG_BITBANGMII | |
62 | #define CONFIG_BITBANGMII_MULTI | |
63 | ||
64 | /* I2C */ | |
65 | #define CONFIG_CMD_I2C | |
66 | #define CONFIG_SH_SH7734_I2C 1 | |
67 | #define CONFIG_HARD_I2C 1 | |
68 | #define CONFIG_I2C_MULTI_BUS 1 | |
69 | #define CONFIG_SYS_MAX_I2C_BUS 2 | |
70 | #define CONFIG_SYS_I2C_MODULE 0 | |
71 | #define CONFIG_SYS_I2C_SPEED 400000 /* 400 kHz */ | |
72 | #define CONFIG_SYS_I2C_SLAVE 0x50 | |
73 | #define CONFIG_SH_I2C_DATA_HIGH 4 | |
74 | #define CONFIG_SH_I2C_DATA_LOW 5 | |
75 | #define CONFIG_SH_I2C_CLOCK 500000000 | |
76 | #define CONFIG_SH_I2C_BASE0 0xFFC70000 | |
77 | #define CONFIG_SH_I2C_BASE1 0xFFC71000 | |
78 | ||
79 | /* undef to save memory */ | |
80 | #define CONFIG_SYS_LONGHELP | |
81 | /* Monitor Command Prompt */ | |
82 | #define CONFIG_SYS_PROMPT "=> " | |
83 | /* Buffer size for input from the Console */ | |
84 | #define CONFIG_SYS_CBSIZE 256 | |
85 | /* Buffer size for Console output */ | |
86 | #define CONFIG_SYS_PBSIZE 256 | |
87 | /* max args accepted for monitor commands */ | |
88 | #define CONFIG_SYS_MAXARGS 16 | |
89 | /* Buffer size for Boot Arguments passed to kernel */ | |
90 | #define CONFIG_SYS_BARGSIZE 512 | |
91 | /* List of legal baudrate settings for this board */ | |
92 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } | |
93 | ||
94 | /* SCIF */ | |
95 | #define CONFIG_SCIF_CONSOLE 1 | |
96 | #define CONFIG_SCIF 1 | |
97 | #define CONFIG_CONS_SCIF4 1 | |
98 | ||
99 | /* Suppress display of console information at boot */ | |
100 | #undef CONFIG_SYS_CONSOLE_INFO_QUIET | |
101 | #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
102 | #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE | |
103 | ||
104 | /* SDRAM */ | |
105 | #define CONFIG_SYS_SDRAM_BASE (0x88000000) | |
106 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) | |
107 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) | |
108 | ||
109 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) | |
110 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE) | |
111 | /* Enable alternate, more extensive, memory test */ | |
112 | #undef CONFIG_SYS_ALT_MEMTEST | |
113 | /* Scratch address used by the alternate memory test */ | |
114 | #undef CONFIG_SYS_MEMTEST_SCRATCH | |
115 | ||
116 | /* Enable temporary baudrate change while serial download */ | |
117 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE | |
118 | ||
119 | /* FLASH */ | |
120 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
121 | #define CONFIG_SYS_FLASH_CFI | |
122 | #undef CONFIG_SYS_FLASH_QUIET_TEST | |
123 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
124 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) | |
125 | #define CONFIG_SYS_MAX_FLASH_SECT 512 | |
126 | ||
127 | /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ | |
128 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
129 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
130 | ||
131 | /* Timeout for Flash erase operations (in ms) */ | |
132 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) | |
133 | /* Timeout for Flash write operations (in ms) */ | |
134 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) | |
135 | /* Timeout for Flash set sector lock bit operations (in ms) */ | |
136 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) | |
137 | /* Timeout for Flash clear lock bit operations (in ms) */ | |
138 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) | |
139 | ||
140 | /* | |
141 | * Use hardware flash sectors protection instead | |
142 | * of U-Boot software protection | |
143 | */ | |
144 | #undef CONFIG_SYS_FLASH_PROTECTION | |
145 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP | |
146 | ||
147 | /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ | |
148 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) | |
149 | /* Monitor size */ | |
150 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
151 | /* Size of DRAM reserved for malloc() use */ | |
152 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) | |
153 | /* size in bytes reserved for initial data */ | |
154 | #define CONFIG_SYS_GBL_DATA_SIZE (256) | |
155 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) | |
156 | ||
157 | /* ENV setting */ | |
158 | #define CONFIG_ENV_IS_IN_FLASH | |
159 | #define CONFIG_ENV_OVERWRITE 1 | |
160 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) | |
161 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
162 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) | |
163 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ | |
164 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) | |
165 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) | |
166 | ||
167 | /* Board Clock */ | |
168 | #if defined(CONFIG_400MHZ_MODE) | |
169 | #define CONFIG_SYS_CLK_FREQ 50000000 | |
170 | #else | |
171 | #define CONFIG_SYS_CLK_FREQ 44444444 | |
172 | #endif | |
173 | #define CONFIG_SYS_TMU_CLK_DIV 4 | |
174 | #define CONFIG_SYS_HZ 1000 | |
175 | ||
176 | #endif /* __AP_SH4A_4A_H */ |