[people/ms/u-boot.git] / include / configs / apf27.h

/*
 *
 * Configuration settings for the Armadeus Project motherboard APF27
 *
 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
 *
 * SPDX-License-Identifier:    GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_ENV_VERSION	10
#define CONFIG_BOARD_NAME apf27

/*
 * SoC configurations
 */
#define CONFIG_MX27			/* This is a Freescale i.MX27 Chip */
#define CONFIG_MACH_TYPE	1698	/* APF27 */

/*
 * Enable the call to miscellaneous platform dependent initialization.
 */

/*
 * SPL
 */
#define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_SIZE	2048
#define CONFIG_SPL_TEXT_BASE    0xA0000000

/* NAND boot config */
#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x800
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_SIZE	CONFIG_SYS_MONITOR_LEN - 0x800

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2

#define CONFIG_HOSTNAME	CONFIG_BOARD_NAME
#define CONFIG_ROOTPATH	"/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"

/*
 * Memory configurations
 */
#define CONFIG_NR_DRAM_POPULATED 1
#define CONFIG_NR_DRAM_BANKS	2

#define ACFG_SDRAM_MBYTE_SYZE 64

#define PHYS_SDRAM_1			0xA0000000
#define PHYS_SDRAM_2			0xB0000000
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (512<<10))
#define CONFIG_SYS_MEMTEST_START	0xA0000000	/* memtest test area  */
#define CONFIG_SYS_MEMTEST_END		0xA0300000	/* 3 MiB RAM test */

#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE	\
		+ PHYS_SDRAM_1_SIZE - 0x0100000)

/*
 * FLASH organization
 */
#define	ACFG_MONITOR_OFFSET		0x00000000
#define	CONFIG_SYS_MONITOR_LEN		0x00100000	/* 1MiB */
#define	CONFIG_ENV_OVERWRITE
#define	CONFIG_ENV_OFFSET		0x00100000	/* NAND offset */
#define	CONFIG_ENV_SIZE			0x00020000	/* 128kB  */
#define CONFIG_ENV_RANGE		0X00080000	/* 512kB */
#define	CONFIG_ENV_OFFSET_REDUND	\
		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)	/* +512kB */
#define	CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE	/* 512kB */
#define	CONFIG_FIRMWARE_OFFSET		0x00200000
#define	CONFIG_FIRMWARE_SIZE		0x00080000	/* 512kB  */
#define	CONFIG_KERNEL_OFFSET		0x00300000
#define	CONFIG_ROOTFS_OFFSET		0x00800000

/*
 * U-Boot general configurations
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE		2048		/* console I/O buffer */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
						/* Boot argument buffer size */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_PREBOOT			"run check_flash check_env;"

/*
 * Boot Linux
 */
#define CONFIG_CMDLINE_TAG		/* send commandline to Kernel	*/
#define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
#define CONFIG_INITRD_TAG		/* send initrd params	*/

#define	CONFIG_BOOTFILE		__stringify(CONFIG_BOARD_NAME) "-linux.bin"

#define ACFG_CONSOLE_DEV	ttySMX0
#define CONFIG_BOOTCOMMAND	"run ubifsboot"
#define CONFIG_SYS_AUTOLOAD	"no"
/*
 * Default load address for user programs and kernel
 */
#define CONFIG_LOADADDR			0xA0000000
#define	CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

/*
 * Extra Environments
 */
#define CONFIG_EXTRA_ENV_SETTINGS \
	"env_version="		__stringify(CONFIG_ENV_VERSION)		"\0" \
	"consoledev="		__stringify(ACFG_CONSOLE_DEV)		"\0" \
	"mtdparts="	 	CONFIG_MTDPARTS_DEFAULT	"\0" \
	"partition=nand0,6\0"						\
	"u-boot_addr="		__stringify(ACFG_MONITOR_OFFSET)	"\0" \
	"env_addr="		__stringify(CONFIG_ENV_OFFSET)		"\0" \
	"firmware_addr="	__stringify(CONFIG_FIRMWARE_OFFSET)	"\0" \
	"firmware_size="	__stringify(CONFIG_FIRMWARE_SIZE)	"\0" \
	"kernel_addr="		__stringify(CONFIG_KERNEL_OFFSET)	"\0" \
	"rootfs_addr="		__stringify(CONFIG_ROOTFS_OFFSET)	"\0" \
	"board_name="		__stringify(CONFIG_BOARD_NAME)		"\0" \
	"kernel_addr_r=A0000000\0" \
	"check_env=if test -n ${flash_env_version}; "			\
		"then env default env_version; "			\
		"else env set flash_env_version ${env_version}; env save; "\
		"fi; "							\
		"if itest ${flash_env_version} < ${env_version}; then " \
			"echo \"*** Warning - Environment version"	\
			" change suggests: run flash_reset_env; reset\"; "\
			"env default flash_reset_env; "\
		"fi; \0"						\
	"check_flash=nand lock; nand unlock ${env_addr}; \0"	\
	"flash_reset_env=env default -f -a; saveenv; run update_env;"	\
		"echo Flash environment variables erased!\0"		\
	"download_uboot=tftpboot ${loadaddr} ${board_name}"		\
		"-u-boot-with-spl.bin\0"				\
	"flash_uboot=nand unlock ${u-boot_addr} ;"			\
		"nand erase.part u-boot;"		\
		"if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
			"then nand lock; nand unlock ${env_addr};"	\
				"echo Flashing of uboot succeed;"	\
			"else echo Flashing of uboot failed;"		\
		"fi; \0"						\
	"update_uboot=run download_uboot flash_uboot\0"			\
	"download_env=tftpboot ${loadaddr} ${board_name}"		\
		"-u-boot-env.txt\0"				\
	"flash_env=env import -t ${loadaddr}; env save; \0"		\
	"update_env=run download_env flash_env\0"			\
	"update_all=run update_env update_uboot\0"			\
	"unlock_regs=mw 10000008 0; mw 10020008 0\0"			\

/*
 * Serial Driver
 */
#define CONFIG_MXC_UART
#define CONFIG_CONS_INDEX		1
#define CONFIG_MXC_UART_BASE		UART1_BASE

/*
 * NOR
 */

/*
 * NAND
 */

#define CONFIG_MXC_NAND_REGS_BASE	0xD8000000
#define CONFIG_SYS_NAND_BASE		CONFIG_MXC_NAND_REGS_BASE
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_PAGE_COUNT	CONFIG_SYS_NAND_BLOCK_SIZE / \
						CONFIG_SYS_NAND_PAGE_SIZE
#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	11
#define NAND_MAX_CHIPS			1

#define CONFIG_FLASH_SHOW_PROGRESS	45
#define CONFIG_SYS_NAND_QUIET		1

/*
 * Partitions & Filsystems
 */
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS

/*
 * Ethernet (on SOC imx FEC)
 */
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR		0x1f
#define CONFIG_MII				/* MII PHY management	*/

/*
 * FPGA
 */
#define CONFIG_FPGA_COUNT		1
#define CONFIG_FPGA_SPARTAN3
#define CONFIG_SYS_FPGA_WAIT		250 /* 250 ms */
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_CHECK_CTRLC
#define CONFIG_SYS_FPGA_CHECK_ERROR

/*
 * Fuses - IIM
 */
#ifdef CONFIG_CMD_IMX_FUSE
#define IIM_MAC_BANK		0
#define IIM_MAC_ROW		5
#define IIM0_SCC_KEY		11
#define IIM1_SUID		1
#endif

/*
 * I2C
 */

#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_MXC_I2C1_SPEED	100000	/* 100 kHz */
#define CONFIG_SYS_MXC_I2C1_SLAVE	0x7F
#define CONFIG_SYS_MXC_I2C2_SPEED	100000	/* 100 kHz */
#define CONFIG_SYS_MXC_I2C2_SLAVE	0x7F
#define CONFIG_SYS_I2C_NOPROBES		{ }

#ifdef CONFIG_CMD_EEPROM
# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24LC02 */
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* msec */
#endif /* CONFIG_CMD_EEPROM */
#endif /* CONFIG_CMD_I2C */

/*
 * SD/MMC
 */
#ifdef CONFIG_CMD_MMC
#define CONFIG_MXC_MCI_REGS_BASE	0x10014000
#endif

/*
 * RTC
 */
#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_DS1374
#define CONFIG_SYS_RTC_BUS_NUM		0
#endif /* CONFIG_CMD_DATE */

/*
 * PLL
 *
 *  31 | x  |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
 *     |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
 */
#define CONFIG_MX27_CLK32		32768	/* 32768 or 32000 Hz crystal */

#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
/* micron 64MB */
#define PHYS_SDRAM_1_SIZE			0x04000000 /* 64 MB */
#define PHYS_SDRAM_2_SIZE			0x04000000 /* 64 MB */
#endif

#if (ACFG_SDRAM_MBYTE_SYZE == 128)
/* micron 128MB */
#define PHYS_SDRAM_1_SIZE			0x08000000 /* 128 MB */
#define PHYS_SDRAM_2_SIZE			0x08000000 /* 128 MB */
#endif

#if (ACFG_SDRAM_MBYTE_SYZE == 256)
/* micron 256MB */
#define PHYS_SDRAM_1_SIZE			0x10000000 /* 256 MB */
#define PHYS_SDRAM_2_SIZE			0x10000000 /* 256 MB */
#endif

#endif /* __CONFIG_H */
Commit	Line	Data
bcc05c7a	1	/*
	2	*
	3	* Configuration settings for the Armadeus Project motherboard APF27
	4	*
	5	* Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
bcc05c7a	13	#define CONFIG_ENV_VERSION 10
bcc05c7a	14	#define CONFIG_BOARD_NAME apf27
	15
	16	/*
	17	* SoC configurations
	18	*/
5d7b131d	19	#define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
bcc05c7a	20	#define CONFIG_MACH_TYPE 1698 /* APF27 */
bcc05c7a	21
	22	/*
	23	* Enable the call to miscellaneous platform dependent initialization.
	24	*/
bcc05c7a	25
bcc05c7a	26	/*
	27	* SPL
	28	*/
bcc05c7a	29	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
bcc05c7a	30	#define CONFIG_SPL_MAX_SIZE 2048
	31	#define CONFIG_SPL_TEXT_BASE 0xA0000000
	32
	33	/* NAND boot config */
bcc05c7a	34	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	35	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
	36	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	37	#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
	38
	39	/*
	40	* BOOTP options
	41	*/
	42	#define CONFIG_BOOTP_SUBNETMASK
	43	#define CONFIG_BOOTP_GATEWAY
	44	#define CONFIG_BOOTP_HOSTNAME
	45	#define CONFIG_BOOTP_BOOTPATH
	46	#define CONFIG_BOOTP_BOOTFILESIZE
	47	#define CONFIG_BOOTP_DNS
	48	#define CONFIG_BOOTP_DNS2
	49
	50	#define CONFIG_HOSTNAME CONFIG_BOARD_NAME
	51	#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
	52
bcc05c7a	53	/*
	54	* Memory configurations
	55	*/
	56	#define CONFIG_NR_DRAM_POPULATED 1
	57	#define CONFIG_NR_DRAM_BANKS 2
	58
	59	#define ACFG_SDRAM_MBYTE_SYZE 64
	60
	61	#define PHYS_SDRAM_1 0xA0000000
	62	#define PHYS_SDRAM_2 0xB0000000
	63	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	64	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
	65	#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
	66	#define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
	67
	68	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
	69	+ PHYS_SDRAM_1_SIZE - 0x0100000)
	70
bcc05c7a	71	/*
	72	* FLASH organization
	73	*/
	74	#define ACFG_MONITOR_OFFSET 0x00000000
	75	#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
bcc05c7a	76	#define CONFIG_ENV_OVERWRITE
	77	#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
	78	#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
	79	#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
	80	#define CONFIG_ENV_OFFSET_REDUND \
	81	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */
	82	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */
	83	#define CONFIG_FIRMWARE_OFFSET 0x00200000
	84	#define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */
	85	#define CONFIG_KERNEL_OFFSET 0x00300000
	86	#define CONFIG_ROOTFS_OFFSET 0x00800000
	87
bcc05c7a	88	/*
	89	* U-Boot general configurations
	90	*/
	91	#define CONFIG_SYS_LONGHELP
bcc05c7a	92	#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
bcc05c7a	93	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	94	/* Boot argument buffer size */
	95	#define CONFIG_AUTO_COMPLETE
	96	#define CONFIG_CMDLINE_EDITING
bcc05c7a	97	#define CONFIG_ENV_VARS_UBOOT_CONFIG
	98	#define CONFIG_PREBOOT "run check_flash check_env;"
	99
bcc05c7a	100	/*
	101	* Boot Linux
	102	*/
	103	#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
	104	#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
	105	#define CONFIG_INITRD_TAG /* send initrd params */
	106
bcc05c7a	107	#define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin"
bcc05c7a	108
	109	#define ACFG_CONSOLE_DEV ttySMX0
	110	#define CONFIG_BOOTCOMMAND "run ubifsboot"
	111	#define CONFIG_SYS_AUTOLOAD "no"
	112	/*
	113	* Default load address for user programs and kernel
	114	*/
	115	#define CONFIG_LOADADDR 0xA0000000
	116	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	117
	118	/*
	119	* Extra Environments
	120	*/
	121	#define CONFIG_EXTRA_ENV_SETTINGS \
	122	"env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \
	123	"consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \
43ede0bc	124	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
bcc05c7a	125	"partition=nand0,6\0" \
	126	"u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \
	127	"env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \
	128	"firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \
	129	"firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \
	130	"kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \
	131	"rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \
	132	"board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \
	133	"kernel_addr_r=A0000000\0" \
	134	"check_env=if test -n ${flash_env_version}; " \
	135	"then env default env_version; " \
	136	"else env set flash_env_version ${env_version}; env save; "\
	137	"fi; " \
	138	"if itest ${flash_env_version} < ${env_version}; then " \
	139	"echo \"*** Warning - Environment version" \
	140	" change suggests: run flash_reset_env; reset\"; "\
	141	"env default flash_reset_env; "\
	142	"fi; \0" \
	143	"check_flash=nand lock; nand unlock ${env_addr}; \0" \
	144	"flash_reset_env=env default -f -a; saveenv; run update_env;" \
	145	"echo Flash environment variables erased!\0" \
	146	"download_uboot=tftpboot ${loadaddr} ${board_name}" \
	147	"-u-boot-with-spl.bin\0" \
	148	"flash_uboot=nand unlock ${u-boot_addr} ;" \
	149	"nand erase.part u-boot;" \
	150	"if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
	151	"then nand lock; nand unlock ${env_addr};" \
	152	"echo Flashing of uboot succeed;" \
	153	"else echo Flashing of uboot failed;" \
	154	"fi; \0" \
	155	"update_uboot=run download_uboot flash_uboot\0" \
	156	"download_env=tftpboot ${loadaddr} ${board_name}" \
	157	"-u-boot-env.txt\0" \
	158	"flash_env=env import -t ${loadaddr}; env save; \0" \
	159	"update_env=run download_env flash_env\0" \
	160	"update_all=run update_env update_uboot\0" \
	161	"unlock_regs=mw 10000008 0; mw 10020008 0\0" \
	162
	163	/*
	164	* Serial Driver
	165	*/
	166	#define CONFIG_MXC_UART
	167	#define CONFIG_CONS_INDEX 1
bcc05c7a	168	#define CONFIG_MXC_UART_BASE UART1_BASE
bcc05c7a	169
bcc05c7a	170	/*
	171	* NOR
	172	*/
	173
	174	/*
	175	* NAND
	176	*/
bcc05c7a	177
	178	#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
	179	#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
	180	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	181
	182	#define CONFIG_MXC_NAND_HWECC
	183	#define CONFIG_SYS_NAND_LARGEPAGE
bcc05c7a	184	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	185	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	186	#define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \
	187	CONFIG_SYS_NAND_PAGE_SIZE
	188	#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
	189	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 11
	190	#define NAND_MAX_CHIPS 1
	191
	192	#define CONFIG_FLASH_SHOW_PROGRESS 45
	193	#define CONFIG_SYS_NAND_QUIET 1
	194
	195	/*
	196	* Partitions & Filsystems
	197	*/
	198	#define CONFIG_MTD_DEVICE
	199	#define CONFIG_MTD_PARTITIONS
bcc05c7a	200
bcc05c7a	201	/*
	202	* Ethernet (on SOC imx FEC)
	203	*/
	204	#define CONFIG_FEC_MXC
	205	#define CONFIG_FEC_MXC_PHYADDR 0x1f
	206	#define CONFIG_MII /* MII PHY management */
	207
b5e7f1bc	208	/*
	209	* FPGA
	210	*/
b5e7f1bc	211	#define CONFIG_FPGA_COUNT 1
b5e7f1bc	212	#define CONFIG_FPGA_SPARTAN3
	213	#define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
	214	#define CONFIG_SYS_FPGA_PROG_FEEDBACK
	215	#define CONFIG_SYS_FPGA_CHECK_CTRLC
	216	#define CONFIG_SYS_FPGA_CHECK_ERROR
	217
bcc05c7a	218	/*
	219	* Fuses - IIM
	220	*/
	221	#ifdef CONFIG_CMD_IMX_FUSE
	222	#define IIM_MAC_BANK 0
	223	#define IIM_MAC_ROW 5
	224	#define IIM0_SCC_KEY 11
	225	#define IIM1_SUID 1
	226	#endif
	227
	228	/*
	229	* I2C
	230	*/
	231
	232	#ifdef CONFIG_CMD_I2C
b089d039	233	#define CONFIG_SYS_I2C
b089d039	234	#define CONFIG_SYS_I2C_MXC
03544c66 AA	235	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	236	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
b089d039	237	#define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */
	238	#define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F
	239	#define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */
	240	#define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F
bcc05c7a	241	#define CONFIG_SYS_I2C_NOPROBES { }
	242
	243	#ifdef CONFIG_CMD_EEPROM
	244	# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
	245	# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
	246	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	247	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
	248	#endif /* CONFIG_CMD_EEPROM */
	249	#endif /* CONFIG_CMD_I2C */
	250
	251	/*
	252	* SD/MMC
	253	*/
	254	#ifdef CONFIG_CMD_MMC
bcc05c7a	255	#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
	256	#endif
	257
	258	/*
	259	* RTC
	260	*/
	261	#ifdef CONFIG_CMD_DATE
	262	#define CONFIG_RTC_DS1374
	263	#define CONFIG_SYS_RTC_BUS_NUM 0
	264	#endif /* CONFIG_CMD_DATE */
	265
bcc05c7a	266	/*
	267	* PLL
	268	*
	269	* 31 \| x \|x\| x x x x \|x x x x x x x x x x \|x x\|x x x x\|x x x x x x x x x x\| 0
	270	* \|CPLM\|X\|----PD---\|--------MFD---------\|XXX\|--MFI--\|-----MFN-----------\|
	271	*/
	272	#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
	273
	274	#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
	275	/* micron 64MB */
	276	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	277	#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
	278	#endif
	279
	280	#if (ACFG_SDRAM_MBYTE_SYZE == 128)
	281	/* micron 128MB */
	282	#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
	283	#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
	284	#endif
	285
	286	#if (ACFG_SDRAM_MBYTE_SYZE == 256)
	287	/* micron 256MB */
	288	#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
	289	#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
	290	#endif
	291
	292	#endif /* __CONFIG_H */