[people/ms/u-boot.git] / include / configs / apollon.h

/*
 * (C) Copyright 2005-2008
 * Samsung Electronics,
 * Kyungmin Park <kyungmin.park@samsung.com>
 *
 * Configuration settings for the 2420 Samsung Apollon board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_ARM1136		1 /* This is an arm1136 CPU core */
#define CONFIG_OMAP		1 /* in a TI OMAP core */
#define CONFIG_OMAP2420		1 /* which is in a 2420 */
#define CONFIG_OMAP2420_APOLLON	1
#define CONFIG_APOLLON		1
#define CONFIG_APOLLON_PLUS	1 /* If you have apollon plus 1.x */

/* Clock config to target*/
#define PRCM_CONFIG_I		1
/* #define PRCM_CONFIG_II	1 */

/* Boot method */
/* uncomment if you use NOR boot */
/* #define CONFIG_SYS_NOR_BOOT		1 */

/* uncomment if you use NOR on CS3 */
/* #define CONFIG_SYS_USE_NOR		1 */

#ifdef CONFIG_SYS_NOR_BOOT
#undef CONFIG_SYS_USE_NOR
#define CONFIG_SYS_USE_NOR		1
#endif

#include <asm/arch/omap2420.h>	/* get chip and board defs */

#define	V_SCLK	12000000

/* input clock of PLL */
/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
#define	CONFIG_SYS_CLK_FREQ	V_SCLK

#undef	CONFIG_USE_IRQ	/* no support for IRQs */
#define	CONFIG_MISC_INIT_R

#define	CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
#define	CONFIG_SETUP_MEMORY_TAGS	1
#define	CONFIG_INITRD_TAG	1
#define	CONFIG_REVISION_TAG	1

/*
 * Size of malloc() pool
 */
#define	CONFIG_ENV_SIZE SZ_128K	/* Total Size of Environment Sector */
#define	CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + SZ_128K)
#define	CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for initial data */

/*
 * Hardware drivers
 */

/*
 * SMC91c96 Etherent
 */
#define	CONFIG_DRIVER_LAN91C96
#define	CONFIG_LAN91C96_BASE	(APOLLON_CS1_BASE+0x300)
#define	CONFIG_LAN91C96_EXT_PHY

/*
 * NS16550 Configuration
 */
#define	V_NS16550_CLK	(48000000)	/* 48MHz (APLL96/2) */

#define	CONFIG_SYS_NS16550
#define	CONFIG_SYS_NS16550_SERIAL
#define	CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define	CONFIG_SYS_NS16550_CLK	V_NS16550_CLK	/* 3MHz (1.5MHz*2) */
#define	CONFIG_SYS_NS16550_COM1	OMAP2420_UART1

/*
 * select serial console configuration
 */
#define	CONFIG_SERIAL1	1	/* UART1 on H4 */

/* allow to overwrite serial and ethaddr */
#define	CONFIG_ENV_OVERWRITE
#define	CONFIG_CONS_INDEX	1
#define	CONFIG_BAUDRATE		115200
#define	CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include	<config_cmd_default.h>

#define	CONFIG_CMD_DHCP
#define	CONFIG_CMD_DIAG
#define	CONFIG_CMD_ONENAND

#undef	CONFIG_CMD_AUTOSCRIPT

#ifndef	CONFIG_SYS_USE_NOR
# undef	CONFIG_CMD_FLASH
# undef	CONFIG_CMD_IMLS
#endif

#define	CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT

#define	CONFIG_BOOTDELAY	1

#define	CONFIG_NETMASK	255.255.255.0
#define	CONFIG_IPADDR	192.168.116.25
#define	CONFIG_SERVERIP	192.168.116.1
#define	CONFIG_BOOTFILE	"uImage"
#define	CONFIG_ETHADDR	00:0E:99:00:24:20

#ifdef	CONFIG_APOLLON_PLUS
# define	CONFIG_BOOTARGS "root=/dev/nfs rw mem=64M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
#else
# define	CONFIG_BOOTARGS "root=/dev/nfs rw mem=128M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"Image=tftp 0x80008000 Image; go 0x80008000\0"			\
	"zImage=tftp 0x80180000 zImage; go 0x80180000\0"		\
	"uImage=tftp 0x80180000 uImage; bootm 0x80180000\0"		\
	"uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0"		\
	"xloader=tftp 0x80180000 x-load.bin; cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0"	\
	"syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0"	\
	"syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0"	\
	"norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0"	\
	"oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0"\
	"onesyncboot=run syncmode oneboot\0"				\
	"updateb=tftp 0x80180000 u-boot-onenand.bin; onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0"					\
	"bootcmd=run uboot\0"

/*
 * Miscellaneous configurable options
 */
#define	V_PROMPT	"Apollon # "

#define	CONFIG_SYS_LONGHELP	/* undef to save memory */
#define	CONFIG_SYS_PROMPT	V_PROMPT
#define	CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define	CONFIG_SYS_MAXARGS	16	/* max number of command args */
#define	CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

#define	CONFIG_SYS_MEMTEST_START	(OMAP2420_SDRC_CS0)	/* memtest works on */
#define	CONFIG_SYS_MEMTEST_END		(OMAP2420_SDRC_CS0+SZ_31M)

#undef	CONFIG_SYS_CLKS_IN_HZ	/* everything, incl board info, in Hz */

#define	CONFIG_SYS_LOAD_ADDR	(OMAP2420_SDRC_CS0)	/* default load address */

/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
 * or by 32KHz clk, or from external sig. This rate is divided by a local
 * divisor.
 */
#define	V_PVT	7	/* use with 12MHz/128 */

#define	CONFIG_SYS_TIMERBASE	OMAP2420_GPT2
#define	CONFIG_SYS_PVT	V_PVT	/* 2^(pvt+1) */
#define	CONFIG_SYS_HZ		((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define	CONFIG_STACKSIZE SZ_128K	/* regular stack */
#ifdef	CONFIG_USE_IRQ
# define	CONFIG_STACKSIZE_IRQ SZ_4K	/* IRQ stack */
# define	CONFIG_STACKSIZE_FIQ SZ_4K	/* FIQ stack */
#endif

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define	CONFIG_NR_DRAM_BANKS	1	/* CS1 may or may not be populated */
#define	PHYS_SDRAM_1		OMAP2420_SDRC_CS0
#define	PHYS_SDRAM_1_SIZE	SZ_128M
#define	PHYS_SDRAM_2		OMAP2420_SDRC_CS1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#ifdef	CONFIG_SYS_USE_NOR
/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */
# define	CONFIG_SYS_FLASH_BASE		0x18000000
# define	CONFIG_SYS_MAX_FLASH_BANKS	1
# define	CONFIG_SYS_MAX_FLASH_SECT	1024
/*-----------------------------------------------------------------------

 * CFI FLASH driver setup
 */
# define	CONFIG_SYS_FLASH_CFI	1	/* Flash memory is CFI compliant */
# define	CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */ /* Use buffered writes (~10x faster) */
# define	CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w sector protection*/

#else	/* !CONFIG_SYS_USE_NOR */
# define	CONFIG_SYS_NO_FLASH	1
#endif	/* CONFIG_SYS_USE_NOR */

/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */
#define	CONFIG_SYS_ONENAND_BASE	0x00000000
#define	CONFIG_ENV_IS_IN_ONENAND	1
#define CONFIG_ENV_ADDR		0x00020000

#endif /* __CONFIG_H */
Commit	Line	Data
5ca9881a	1	/*
8af657d2	2	* (C) Copyright 2005-2008
5ca9881a PP	3	* Samsung Electronics,
	4	* Kyungmin Park <kyungmin.park@samsung.com>
	5	*
	6	* Configuration settings for the 2420 Samsung Apollon board.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*
	31	* High Level Configuration Options
	32	*/
	33	#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
	34	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	35	#define CONFIG_OMAP2420 1 /* which is in a 2420 */
	36	#define CONFIG_OMAP2420_APOLLON 1
	37	#define CONFIG_APOLLON 1
	38	#define CONFIG_APOLLON_PLUS 1 /* If you have apollon plus 1.x */
	39
	40	/* Clock config to target*/
	41	#define PRCM_CONFIG_I 1
435dc8fc	42	/* #define PRCM_CONFIG_II 1 */
5ca9881a PP	43
	44	/* Boot method */
	45	/* uncomment if you use NOR boot */
6d0f6bcf	46	/* #define CONFIG_SYS_NOR_BOOT 1 */
5ca9881a PP	47
5ca9881a PP	48	/* uncomment if you use NOR on CS3 */
6d0f6bcf	49	/* #define CONFIG_SYS_USE_NOR 1 */
5ca9881a	50
6d0f6bcf JCPV	51	#ifdef CONFIG_SYS_NOR_BOOT
	52	#undef CONFIG_SYS_USE_NOR
	53	#define CONFIG_SYS_USE_NOR 1
5ca9881a PP	54	#endif
	55
	56	#include <asm/arch/omap2420.h> /* get chip and board defs */
	57
	58	#define V_SCLK 12000000
	59
	60	/* input clock of PLL */
	61	/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
	62	#define CONFIG_SYS_CLK_FREQ V_SCLK
	63
	64	#undef CONFIG_USE_IRQ /* no support for IRQs */
	65	#define CONFIG_MISC_INIT_R
	66
	67	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	68	#define CONFIG_SETUP_MEMORY_TAGS 1
	69	#define CONFIG_INITRD_TAG 1
	70	#define CONFIG_REVISION_TAG 1
	71
	72	/*
	73	* Size of malloc() pool
	74	*/
0e8d1586	75	#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
6d0f6bcf JCPV	76	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
6d0f6bcf JCPV	77	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
5ca9881a PP	78
	79	/*
	80	* Hardware drivers
	81	*/
	82
	83	/*
	84	* SMC91c96 Etherent
	85	*/
	86	#define CONFIG_DRIVER_LAN91C96
	87	#define CONFIG_LAN91C96_BASE (APOLLON_CS1_BASE+0x300)
	88	#define CONFIG_LAN91C96_EXT_PHY
	89
	90	/*
	91	* NS16550 Configuration
	92	*/
	93	#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
	94
6d0f6bcf JCPV	95	#define CONFIG_SYS_NS16550
	96	#define CONFIG_SYS_NS16550_SERIAL
	97	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	98	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz2) /
	99	#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1
5ca9881a PP	100
	101	/*
	102	* select serial console configuration
	103	*/
	104	#define CONFIG_SERIAL1 1 /* UART1 on H4 */
	105
435dc8fc	106	/* allow to overwrite serial and ethaddr */
5ca9881a PP	107	#define CONFIG_ENV_OVERWRITE
	108	#define CONFIG_CONS_INDEX 1
	109	#define CONFIG_BAUDRATE 115200
6d0f6bcf	110	#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
5ca9881a	111
435dc8fc	112	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
5ca9881a PP	113	#include <config_cmd_default.h>
	114
	115	#define CONFIG_CMD_DHCP
	116	#define CONFIG_CMD_DIAG
	117	#define CONFIG_CMD_ONENAND
	118
	119	#undef CONFIG_CMD_AUTOSCRIPT
	120
6d0f6bcf	121	#ifndef CONFIG_SYS_USE_NOR
5ca9881a PP	122	# undef CONFIG_CMD_FLASH
	123	# undef CONFIG_CMD_IMLS
	124	#endif
	125
	126	#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
	127
	128	#define CONFIG_BOOTDELAY 1
	129
	130	#define CONFIG_NETMASK 255.255.255.0
	131	#define CONFIG_IPADDR 192.168.116.25
	132	#define CONFIG_SERVERIP 192.168.116.1
	133	#define CONFIG_BOOTFILE "uImage"
	134	#define CONFIG_ETHADDR 00:0E:99:00:24:20
	135
	136	#ifdef CONFIG_APOLLON_PLUS
	137	# define CONFIG_BOOTARGS "root=/dev/nfs rw mem=64M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
	138	#else
	139	# define CONFIG_BOOTARGS "root=/dev/nfs rw mem=128M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
	140	#endif
	141
	142	#define CONFIG_EXTRA_ENV_SETTINGS \
2ae64f51 PP	143	"Image=tftp 0x80008000 Image; go 0x80008000\0" \
	144	"zImage=tftp 0x80180000 zImage; go 0x80180000\0" \
	145	"uImage=tftp 0x80180000 uImage; bootm 0x80180000\0" \
	146	"uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0" \
	147	"xloader=tftp 0x80180000 x-load.bin; cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0" \
	148	"syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0" \
	149	"syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0" \
	150	"norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0" \
	151	"oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0"\
5ca9881a	152	"onesyncboot=run syncmode oneboot\0" \
8af657d2	153	"updateb=tftp 0x80180000 u-boot-onenand.bin; onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0" \
5ca9881a PP	154	"bootcmd=run uboot\0"
	155
	156	/*
	157	* Miscellaneous configurable options
	158	*/
	159	#define V_PROMPT "Apollon # "
	160
6d0f6bcf JCPV	161	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	162	#define CONFIG_SYS_PROMPT V_PROMPT
	163	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
5ca9881a	164	/* Print Buffer Size */
6d0f6bcf JCPV	165	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	166	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	167	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
5ca9881a	168
6d0f6bcf JCPV	169	#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
6d0f6bcf JCPV	170	#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
5ca9881a	171
6d0f6bcf	172	#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
5ca9881a	173
6d0f6bcf	174	#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
5ca9881a	175
435dc8fc WD	176	/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
435dc8fc WD	177	* or by 32KHz clk, or from external sig. This rate is divided by a local
5ca9881a PP	178	* divisor.
	179	*/
	180	#define V_PVT 7 /* use with 12MHz/128 */
	181
6d0f6bcf JCPV	182	#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
	183	#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
	184	#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
5ca9881a PP	185
	186	/*-----------------------------------------------------------------------
	187	* Stack sizes
	188	*
435dc8fc	189	* The stack sizes are set up in start.S using the settings below
5ca9881a PP	190	*/
	191	#define CONFIG_STACKSIZE SZ_128K /* regular stack */
	192	#ifdef CONFIG_USE_IRQ
	193	# define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
	194	# define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
	195	#endif
	196
	197	/*-----------------------------------------------------------------------
	198	* Physical Memory Map
	199	*/
	200	#define CONFIG_NR_DRAM_BANKS 1 /* CS1 may or may not be populated */
	201	#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
	202	#define PHYS_SDRAM_1_SIZE SZ_128M
	203	#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
	204
	205	/*-----------------------------------------------------------------------
	206	* FLASH and environment organization
	207	*/
6d0f6bcf	208	#ifdef CONFIG_SYS_USE_NOR
5ca9881a	209	/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */
6d0f6bcf JCPV	210	# define CONFIG_SYS_FLASH_BASE 0x18000000
	211	# define CONFIG_SYS_MAX_FLASH_BANKS 1
	212	# define CONFIG_SYS_MAX_FLASH_SECT 1024
5ca9881a PP	213	/*-----------------------------------------------------------------------
	214
	215	* CFI FLASH driver setup
	216	*/
6d0f6bcf	217	# define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
00b1883a	218	# define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
6d0f6bcf JCPV	219	/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 / / Use buffered writes (~10x faster) */
6d0f6bcf JCPV	220	# define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w sector protection*/
5ca9881a	221
6d0f6bcf JCPV	222	#else /* !CONFIG_SYS_USE_NOR */
	223	# define CONFIG_SYS_NO_FLASH 1
	224	#endif /* CONFIG_SYS_USE_NOR */
5ca9881a PP	225
5ca9881a PP	226	/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */
6d0f6bcf	227	#define CONFIG_SYS_ONENAND_BASE 0x00000000
9656138f	228	#define CONFIG_ENV_IS_IN_ONENAND 1
0e8d1586	229	#define CONFIG_ENV_ADDR 0x00020000
5ca9881a PP	230
5ca9881a PP	231	#endif /* __CONFIG_H */