[people/ms/u-boot.git] / include / configs / apollon.h

/*
 * (C) Copyright 2005-2008
 * Samsung Electronics,
 * Kyungmin Park <kyungmin.park@samsung.com>
 *
 * Configuration settings for the 2420 Samsung Apollon board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_ARM1136		1 /* This is an arm1136 CPU core */
#define CONFIG_OMAP		1 /* in a TI OMAP core */
#define CONFIG_OMAP2420		1 /* which is in a 2420 */
#define CONFIG_OMAP2420_APOLLON	1
#define CONFIG_APOLLON		1
#define CONFIG_APOLLON_PLUS	1 /* If you have apollon plus 1.x */

#define CONFIG_ONENAND_U_BOOT	y

/* Clock config to target*/
#define PRCM_CONFIG_I		1
/* #define PRCM_CONFIG_II	1 */

/* Boot method */
/* uncomment if you use NOR boot */
/* #define CONFIG_SYS_NOR_BOOT		1 */

/* uncomment if you use NOR on CS3 */
/* #define CONFIG_SYS_USE_NOR		1 */

#ifdef CONFIG_SYS_NOR_BOOT
#undef CONFIG_SYS_USE_NOR
#define CONFIG_SYS_USE_NOR		1
#endif

/* uncommnet if you want to use UBI */
#define CONFIG_SYS_USE_UBI

#include <asm/arch/omap2420.h>	/* get chip and board defs */

#define	V_SCLK	12000000

/* input clock of PLL */
/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
#define	CONFIG_SYS_CLK_FREQ	V_SCLK

#define	CONFIG_MISC_INIT_R

#define	CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
#define	CONFIG_SETUP_MEMORY_TAGS	1
#define	CONFIG_INITRD_TAG	1
#define	CONFIG_REVISION_TAG	1

/*
 * Size of malloc() pool
 */
#define	CONFIG_ENV_SIZE SZ_128K	/* Total Size of Environment Sector */
#define CONFIG_ENV_SIZE_FLEX SZ_256K
#define	CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + SZ_1M)

/*
 * Hardware drivers
 */

/*
 * SMC91c96 Etherent
 */
#define	CONFIG_LAN91C96
#define	CONFIG_LAN91C96_BASE	(APOLLON_CS1_BASE+0x300)
#define	CONFIG_LAN91C96_EXT_PHY

/*
 * NS16550 Configuration
 */
#define	V_NS16550_CLK	(48000000)	/* 48MHz (APLL96/2) */

#define	CONFIG_SYS_NS16550
#define	CONFIG_SYS_NS16550_SERIAL
#define	CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define	CONFIG_SYS_NS16550_CLK	V_NS16550_CLK	/* 3MHz (1.5MHz*2) */
#define	CONFIG_SYS_NS16550_COM1	OMAP2420_UART1

/*
 * select serial console configuration
 */
#define	CONFIG_SERIAL1	1	/* UART1 on H4 */

/* allow to overwrite serial and ethaddr */
#define	CONFIG_ENV_OVERWRITE
#define	CONFIG_CONS_INDEX	1
#define	CONFIG_BAUDRATE		115200

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include	<config_cmd_default.h>

#define	CONFIG_CMD_DHCP
#define	CONFIG_CMD_DIAG
#define	CONFIG_CMD_ONENAND

#ifdef CONFIG_SYS_USE_UBI
#define	CONFIG_CMD_JFFS2
#define	CONFIG_CMD_UBI
#define	CONFIG_RBTREE
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#endif

#undef	CONFIG_CMD_SOURCE

#ifndef	CONFIG_SYS_USE_NOR
# undef	CONFIG_CMD_FLASH
# undef	CONFIG_CMD_IMLS
#endif

#define	CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT

#define	CONFIG_BOOTDELAY	1

#define	CONFIG_NETMASK	255.255.255.0
#define	CONFIG_IPADDR	192.168.116.25
#define	CONFIG_SERVERIP	192.168.116.1
#define	CONFIG_BOOTFILE	"uImage"
#define	CONFIG_ETHADDR	00:0E:99:00:24:20

#ifdef CONFIG_APOLLON_PLUS
#define CONFIG_SYS_MEM	"mem=64M"
#else
#define CONFIG_SYS_MEM	"mem=128"
#endif

#ifdef CONFIG_SYS_USE_UBI
#define CONFIG_SYS_UBI "ubi.mtd=4"
#else
#define CONFIG_SYS_UBI ""
#endif

#define CONFIG_BOOTARGS "root=/dev/nfs rw " CONFIG_SYS_MEM \
	" console=ttyS0,115200n8" \
	" ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:" \
	"apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2 " \
	CONFIG_SYS_UBI

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"Image=tftp 0x80008000 Image; go 0x80008000\0"			\
	"zImage=tftp 0x80180000 zImage; go 0x80180000\0"		\
	"uImage=tftp 0x80180000 uImage; bootm 0x80180000\0"		\
	"uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0"		\
	"xloader=tftp 0x80180000 x-load.bin; "				\
	" cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0"		\
	"syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0"	\
	"syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0"	\
	"norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0"	\
	"oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0" \
	"onesyncboot=run syncmode oneboot\0"				\
	"updateb=tftp 0x80180000 u-boot-onenand.bin; "			\
	" onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0" \
	"ubi=setenv bootargs ${bootargs} ubi.mtd=4 ${mtdparts}; run uImage\0" \
	"bootcmd=run uboot\0"

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP	/* undef to save memory */
#define	CONFIG_SYS_PROMPT	"Apollon # "
#define	CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define	CONFIG_SYS_MAXARGS	16	/* max number of command args */
/* Boot Argument Buffer Size */
#define	CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
/* memtest works on */
#define	CONFIG_SYS_MEMTEST_START	(OMAP2420_SDRC_CS0)
#define	CONFIG_SYS_MEMTEST_END		(OMAP2420_SDRC_CS0+SZ_31M)

/* default load address */
#define	CONFIG_SYS_LOAD_ADDR	(OMAP2420_SDRC_CS0)

/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
 * or by 32KHz clk, or from external sig. This rate is divided by a local
 * divisor.
 */
#define	CONFIG_SYS_TIMERBASE	OMAP2420_GPT2
#define	CONFIG_SYS_PTV		7	/* 2^(PTV+1) */
#define	CONFIG_SYS_HZ		((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define	CONFIG_NR_DRAM_BANKS	1	/* CS1 may or may not be populated */
#define	PHYS_SDRAM_1		OMAP2420_SDRC_CS0
#define	PHYS_SDRAM_1_SIZE	SZ_128M
#define	PHYS_SDRAM_2		OMAP2420_SDRC_CS1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#ifdef	CONFIG_SYS_USE_NOR
/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */
# define	CONFIG_SYS_FLASH_BASE		0x18000000
# define	CONFIG_SYS_MAX_FLASH_BANKS	1
# define	CONFIG_SYS_MAX_FLASH_SECT	1024
/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* Flash memory is CFI compliant */
# define	CONFIG_SYS_FLASH_CFI	1
# define	CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
/* Use buffered writes (~10x faster) */
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */
/* Use h/w sector protection*/
# define	CONFIG_SYS_FLASH_PROTECTION	1

#else	/* !CONFIG_SYS_USE_NOR */
# define	CONFIG_SYS_NO_FLASH	1
#endif	/* CONFIG_SYS_USE_NOR */

/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */
#define	CONFIG_SYS_ONENAND_BASE	0x00000000
#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* U-Boot image size */
#define	CONFIG_ENV_IS_IN_ONENAND	1
#define CONFIG_ENV_ADDR		0x00020000
#define CONFIG_ENV_ADDR_FLEX	0x00040000

#ifdef CONFIG_SYS_USE_UBI
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT		"onenand0=onenand"
#define MTDPARTS_DEFAULT	"mtdparts=onenand:128k(bootloader),"	\
					"128k(params),"			\
					"2m(kernel),"			\
					"16m(rootfs),"			\
					"32m(fs),"			\
					"-(ubifs)"
#endif

#define PHYS_SRAM			0x4020F800
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR 	PHYS_SRAM

#endif /* __CONFIG_H */
Commit	Line	Data
5ca9881a	1	/*
8af657d2	2	* (C) Copyright 2005-2008
5ca9881a PP	3	* Samsung Electronics,
	4	* Kyungmin Park <kyungmin.park@samsung.com>
	5	*
	6	* Configuration settings for the 2420 Samsung Apollon board.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*
	31	* High Level Configuration Options
	32	*/
	33	#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
	34	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	35	#define CONFIG_OMAP2420 1 /* which is in a 2420 */
	36	#define CONFIG_OMAP2420_APOLLON 1
	37	#define CONFIG_APOLLON 1
	38	#define CONFIG_APOLLON_PLUS 1 /* If you have apollon plus 1.x */
	39
a276db28 WD	40	#define CONFIG_ONENAND_U_BOOT y
a276db28 WD	41
5ca9881a PP	42	/* Clock config to target*/
5ca9881a PP	43	#define PRCM_CONFIG_I 1
435dc8fc	44	/* #define PRCM_CONFIG_II 1 */
5ca9881a PP	45
	46	/* Boot method */
	47	/* uncomment if you use NOR boot */
6d0f6bcf	48	/* #define CONFIG_SYS_NOR_BOOT 1 */
5ca9881a PP	49
5ca9881a PP	50	/* uncomment if you use NOR on CS3 */
6d0f6bcf	51	/* #define CONFIG_SYS_USE_NOR 1 */
5ca9881a	52
6d0f6bcf JCPV	53	#ifdef CONFIG_SYS_NOR_BOOT
	54	#undef CONFIG_SYS_USE_NOR
	55	#define CONFIG_SYS_USE_NOR 1
5ca9881a PP	56	#endif
5ca9881a PP	57
8000b086 KP	58	/* uncommnet if you want to use UBI */
	59	#define CONFIG_SYS_USE_UBI
	60
5ca9881a PP	61	#include <asm/arch/omap2420.h> /* get chip and board defs */
	62
	63	#define V_SCLK 12000000
	64
	65	/* input clock of PLL */
	66	/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
	67	#define CONFIG_SYS_CLK_FREQ V_SCLK
	68
5ca9881a PP	69	#define CONFIG_MISC_INIT_R
	70
	71	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	72	#define CONFIG_SETUP_MEMORY_TAGS 1
	73	#define CONFIG_INITRD_TAG 1
	74	#define CONFIG_REVISION_TAG 1
	75
	76	/*
	77	* Size of malloc() pool
	78	*/
0e8d1586	79	#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
c758e947	80	#define CONFIG_ENV_SIZE_FLEX SZ_256K
8000b086	81	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_1M)
5ca9881a PP	82
	83	/*
	84	* Hardware drivers
	85	*/
	86
	87	/*
	88	* SMC91c96 Etherent
	89	*/
ac6b362a	90	#define CONFIG_LAN91C96
5ca9881a PP	91	#define CONFIG_LAN91C96_BASE (APOLLON_CS1_BASE+0x300)
	92	#define CONFIG_LAN91C96_EXT_PHY
	93
	94	/*
	95	* NS16550 Configuration
	96	*/
	97	#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
	98
6d0f6bcf JCPV	99	#define CONFIG_SYS_NS16550
	100	#define CONFIG_SYS_NS16550_SERIAL
	101	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	102	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz2) /
	103	#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1
5ca9881a PP	104
	105	/*
	106	* select serial console configuration
	107	*/
	108	#define CONFIG_SERIAL1 1 /* UART1 on H4 */
	109
435dc8fc	110	/* allow to overwrite serial and ethaddr */
5ca9881a PP	111	#define CONFIG_ENV_OVERWRITE
	112	#define CONFIG_CONS_INDEX 1
	113	#define CONFIG_BAUDRATE 115200
5ca9881a	114
435dc8fc	115	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
5ca9881a PP	116	#include <config_cmd_default.h>
	117
	118	#define CONFIG_CMD_DHCP
	119	#define CONFIG_CMD_DIAG
	120	#define CONFIG_CMD_ONENAND
	121
8000b086 KP	122	#ifdef CONFIG_SYS_USE_UBI
	123	#define CONFIG_CMD_JFFS2
	124	#define CONFIG_CMD_UBI
	125	#define CONFIG_RBTREE
942556a9	126	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
8000b086 KP	127	#define CONFIG_MTD_PARTITIONS
	128	#endif
	129
74de7aef	130	#undef CONFIG_CMD_SOURCE
5ca9881a	131
6d0f6bcf	132	#ifndef CONFIG_SYS_USE_NOR
5ca9881a PP	133	# undef CONFIG_CMD_FLASH
	134	# undef CONFIG_CMD_IMLS
	135	#endif
	136
	137	#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
	138
	139	#define CONFIG_BOOTDELAY 1
	140
	141	#define CONFIG_NETMASK 255.255.255.0
	142	#define CONFIG_IPADDR 192.168.116.25
	143	#define CONFIG_SERVERIP 192.168.116.1
	144	#define CONFIG_BOOTFILE "uImage"
	145	#define CONFIG_ETHADDR 00:0E:99:00:24:20
	146
8000b086 KP	147	#ifdef CONFIG_APOLLON_PLUS
	148	#define CONFIG_SYS_MEM "mem=64M"
	149	#else
	150	#define CONFIG_SYS_MEM "mem=128"
	151	#endif
	152
	153	#ifdef CONFIG_SYS_USE_UBI
	154	#define CONFIG_SYS_UBI "ubi.mtd=4"
5ca9881a	155	#else
8000b086	156	#define CONFIG_SYS_UBI ""
5ca9881a PP	157	#endif
5ca9881a PP	158
8000b086 KP	159	#define CONFIG_BOOTARGS "root=/dev/nfs rw " CONFIG_SYS_MEM \
	160	" console=ttyS0,115200n8" \
	161	" ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:" \
	162	"apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2 " \
	163	CONFIG_SYS_UBI
	164
5ca9881a	165	#define CONFIG_EXTRA_ENV_SETTINGS \
2ae64f51 PP	166	"Image=tftp 0x80008000 Image; go 0x80008000\0" \
	167	"zImage=tftp 0x80180000 zImage; go 0x80180000\0" \
	168	"uImage=tftp 0x80180000 uImage; bootm 0x80180000\0" \
	169	"uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0" \
8000b086 KP	170	"xloader=tftp 0x80180000 x-load.bin; " \
8000b086 KP	171	" cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0" \
2ae64f51 PP	172	"syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0" \
	173	"syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0" \
	174	"norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0" \
8000b086	175	"oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0" \
5ca9881a	176	"onesyncboot=run syncmode oneboot\0" \
8000b086 KP	177	"updateb=tftp 0x80180000 u-boot-onenand.bin; " \
	178	" onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0" \
	179	"ubi=setenv bootargs ${bootargs} ubi.mtd=4 ${mtdparts}; run uImage\0" \
5ca9881a PP	180	"bootcmd=run uboot\0"
	181
	182	/*
	183	* Miscellaneous configurable options
	184	*/
6d0f6bcf	185	#define CONFIG_SYS_LONGHELP /* undef to save memory */
1270ec13	186	#define CONFIG_SYS_PROMPT "Apollon # "
6d0f6bcf	187	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
5ca9881a	188	/* Print Buffer Size */
6d0f6bcf JCPV	189	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
6d0f6bcf JCPV	190	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
8000b086 KP	191	/* Boot Argument Buffer Size */
	192	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	193	/* memtest works on */
	194	#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0)
6d0f6bcf	195	#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
5ca9881a	196
8000b086 KP	197	/* default load address */
8000b086 KP	198	#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0)
5ca9881a	199
435dc8fc WD	200	/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
435dc8fc WD	201	* or by 32KHz clk, or from external sig. This rate is divided by a local
5ca9881a PP	202	* divisor.
5ca9881a PP	203	*/
6d0f6bcf	204	#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
81472d89 LM	205	#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
81472d89 LM	206	#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
5ca9881a	207
5ca9881a PP	208	/*-----------------------------------------------------------------------
	209	* Physical Memory Map
	210	*/
	211	#define CONFIG_NR_DRAM_BANKS 1 /* CS1 may or may not be populated */
	212	#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
	213	#define PHYS_SDRAM_1_SIZE SZ_128M
	214	#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
	215
	216	/*-----------------------------------------------------------------------
	217	* FLASH and environment organization
	218	*/
6d0f6bcf	219	#ifdef CONFIG_SYS_USE_NOR
5ca9881a	220	/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */
6d0f6bcf JCPV	221	# define CONFIG_SYS_FLASH_BASE 0x18000000
	222	# define CONFIG_SYS_MAX_FLASH_BANKS 1
	223	# define CONFIG_SYS_MAX_FLASH_SECT 1024
5ca9881a	224	/*-----------------------------------------------------------------------
5ca9881a PP	225	* CFI FLASH driver setup
5ca9881a PP	226	*/
8000b086 KP	227	/* Flash memory is CFI compliant */
8000b086 KP	228	# define CONFIG_SYS_FLASH_CFI 1
00b1883a	229	# define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
8000b086 KP	230	/* Use buffered writes (~10x faster) */
	231	/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */
	232	/* Use h/w sector protection*/
	233	# define CONFIG_SYS_FLASH_PROTECTION 1
5ca9881a	234
6d0f6bcf JCPV	235	#else /* !CONFIG_SYS_USE_NOR */
	236	# define CONFIG_SYS_NO_FLASH 1
	237	#endif /* CONFIG_SYS_USE_NOR */
5ca9881a PP	238
5ca9881a PP	239	/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */
6d0f6bcf	240	#define CONFIG_SYS_ONENAND_BASE 0x00000000
12a67531	241	#define CONFIG_SYS_MONITOR_LEN SZ_256K /* U-Boot image size */
9656138f	242	#define CONFIG_ENV_IS_IN_ONENAND 1
0e8d1586	243	#define CONFIG_ENV_ADDR 0x00020000
c758e947	244	#define CONFIG_ENV_ADDR_FLEX 0x00040000
5ca9881a	245
8000b086	246	#ifdef CONFIG_SYS_USE_UBI
68d7d651	247	#define CONFIG_CMD_MTDPARTS
8000b086 KP	248	#define MTDIDS_DEFAULT "onenand0=onenand"
	249	#define MTDPARTS_DEFAULT "mtdparts=onenand:128k(bootloader)," \
	250	"128k(params)," \
	251	"2m(kernel)," \
	252	"16m(rootfs)," \
	253	"32m(fs)," \
	254	"-(ubifs)"
	255	#endif
	256
0aeb01d5 IG	257	#define PHYS_SRAM 0x4020F800
	258	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	259	#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
	260
5ca9881a	261	#endif /* __CONFIG_H */