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52568c36 WD |
1 | /* |
2 | * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> | |
3 | * (C) Copyright 2009, DAVE Srl <www.dave.eu> | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
52568c36 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * Aria board configuration file | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | #define CONFIG_ARIA 1 | |
32ff89dc | 16 | |
52568c36 WD |
17 | /* |
18 | * Memory map for the ARIA board: | |
19 | * | |
20 | * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB) | |
21 | * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB) | |
22 | * 0x3010_0000-0x3011_FFFF On Board SRAM (128 KB) - CS6 | |
23 | * 0x3020_0000-0x3021_FFFF FPGA (128 KB) - CS2 | |
24 | * 0x8000_0000-0x803F_FFFF IMMR (4 MB) | |
25 | * 0x8400_0000-0x82FF_FFFF PCI I/O space (16 MB) | |
26 | * 0xA000_0000-0xAFFF_FFFF PCI memory space (256 MB) | |
27 | * 0xB000_0000-0xBFFF_FFFF PCI memory mapped I/O space (256 MB) | |
28 | * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB) | |
29 | */ | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | */ | |
34 | #define CONFIG_E300 1 /* E300 Family */ | |
52568c36 | 35 | #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ |
52568c36 | 36 | |
2ae18241 WD |
37 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
38 | ||
52568c36 | 39 | /* video */ |
52568c36 WD |
40 | |
41 | #if defined(CONFIG_VIDEO) | |
52568c36 WD |
42 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
43 | #endif | |
44 | ||
45 | /* CONFIG_PCI is defined at config time */ | |
46 | ||
47 | #define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */ | |
48 | ||
52568c36 WD |
49 | #define CONFIG_MISC_INIT_R |
50 | ||
51 | #define CONFIG_SYS_IMMR 0x80000000 | |
52 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) | |
53 | ||
54 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ | |
55 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
56 | ||
57 | /* | |
58 | * DDR Setup - manually set all parameters as there's no SPD etc. | |
59 | */ | |
60 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ | |
61 | #define CONFIG_SYS_DDR_BASE 0x00000000 | |
62 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
b9947bbb | 63 | #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 |
52568c36 | 64 | |
5d937e8b AG |
65 | #define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 |
66 | ||
52568c36 WD |
67 | /* DDR Controller Configuration |
68 | * | |
69 | * SYS_CFG: | |
70 | * [31:31] MDDRC Soft Reset: Diabled | |
71 | * [30:30] DRAM CKE pin: Enabled | |
72 | * [29:29] DRAM CLK: Enabled | |
73 | * [28:28] Command Mode: Enabled (For initialization only) | |
74 | * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] | |
75 | * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] | |
76 | * [20:19] Read Test: DON'T USE | |
77 | * [18:18] Self Refresh: Enabled | |
78 | * [17:17] 16bit Mode: Disabled | |
79 | * [16:13] Ready Delay: 2 | |
80 | * [12:12] Half DQS Delay: Disabled | |
81 | * [11:11] Quarter DQS Delay: Disabled | |
82 | * [10:08] Write Delay: 2 | |
83 | * [07:07] Early ODT: Disabled | |
84 | * [06:06] On DIE Termination: Disabled | |
85 | * [05:05] FIFO Overflow Clear: DON'T USE here | |
86 | * [04:04] FIFO Underflow Clear: DON'T USE here | |
87 | * [03:03] FIFO Overflow Pending: DON'T USE here | |
88 | * [02:02] FIFO Underlfow Pending: DON'T USE here | |
89 | * [01:01] FIFO Overlfow Enabled: Enabled | |
90 | * [00:00] FIFO Underflow Enabled: Enabled | |
91 | * TIME_CFG0 | |
92 | * [31:16] DRAM Refresh Time: 0 CSB clocks | |
93 | * [15:8] DRAM Command Time: 0 CSB clocks | |
94 | * [07:00] DRAM Precharge Time: 0 CSB clocks | |
95 | * TIME_CFG1 | |
96 | * [31:26] DRAM tRFC: | |
97 | * [25:21] DRAM tWR1: | |
98 | * [20:17] DRAM tWRT1: | |
99 | * [16:11] DRAM tDRR: | |
100 | * [10:05] DRAM tRC: | |
101 | * [04:00] DRAM tRAS: | |
102 | * TIME_CFG2 | |
103 | * [31:28] DRAM tRCD: | |
104 | * [27:23] DRAM tFAW: | |
105 | * [22:19] DRAM tRTW1: | |
106 | * [18:15] DRAM tCCD: | |
107 | * [14:10] DRAM tRTP: | |
108 | * [09:05] DRAM tRP: | |
109 | * [04:00] DRAM tRPA | |
110 | */ | |
25671c86 WD |
111 | #define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \ |
112 | (1 << 30) | /* CKE */ \ | |
113 | (1 << 29) | /* CLK_ON */ \ | |
054197ba | 114 | (0 << 28) | /* CMD_MODE */ \ |
25671c86 WD |
115 | (4 << 25) | /* DRAM_ROW_SELECT */ \ |
116 | (3 << 21) | /* DRAM_BANK_SELECT */ \ | |
117 | (0 << 18) | /* SELF_REF_EN */ \ | |
118 | (0 << 17) | /* 16BIT_MODE */ \ | |
119 | (2 << 13) | /* RDLY */ \ | |
120 | (0 << 12) | /* HALF_DQS_DLY */ \ | |
121 | (1 << 11) | /* QUART_DQS_DLY */ \ | |
122 | (2 << 8) | /* WDLY */ \ | |
123 | (0 << 7) | /* EARLY_ODT */ \ | |
124 | (1 << 6) | /* ON_DIE_TERMINATE */ \ | |
125 | (0 << 5) | /* FIFO_OV_CLEAR */ \ | |
126 | (0 << 4) | /* FIFO_UV_CLEAR */ \ | |
127 | (0 << 1) | /* FIFO_OV_EN */ \ | |
128 | (0 << 0) /* FIFO_UV_EN */ \ | |
129 | ) | |
130 | ||
054197ba | 131 | #define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E |
25671c86 WD |
132 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 |
133 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 | |
52568c36 | 134 | |
054197ba MS |
135 | #define CONFIG_SYS_DDRCMD_NOP 0x01380000 |
136 | #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 | |
25671c86 WD |
137 | #define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ |
138 | (0 << 22) | /* DRAM_CS */ \ | |
139 | (0 << 21) | /* DRAM_RAS */ \ | |
140 | (0 << 20) | /* DRAM_CAS */ \ | |
141 | (0 << 19) | /* DRAM_WEB */ \ | |
142 | (1 << 16) | /* DRAM_BS[2:0] */ \ | |
143 | (0 << 15) | /* */ \ | |
144 | (0 << 12) | /* A12->out */ \ | |
145 | (0 << 11) | /* A11->RDQS */ \ | |
146 | (0 << 10) | /* A10->DQS# */ \ | |
147 | (0 << 7) | /* OCD program */ \ | |
148 | (0 << 6) | /* Rtt1 */ \ | |
149 | (0 << 3) | /* posted CAS# */ \ | |
150 | (0 << 2) | /* Rtt0 */ \ | |
151 | (1 << 1) | /* ODS */ \ | |
152 | (0 << 0) /* DLL */ \ | |
153 | ) | |
154 | #define CONFIG_SYS_MICRON_EMR2 0x01020000 | |
155 | #define CONFIG_SYS_MICRON_EMR3 0x01030000 | |
054197ba | 156 | #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 |
52568c36 | 157 | #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 |
25671c86 WD |
158 | #define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \ |
159 | (0 << 22) | /* DRAM_CS */ \ | |
160 | (0 << 21) | /* DRAM_RAS */ \ | |
161 | (0 << 20) | /* DRAM_CAS */ \ | |
162 | (0 << 19) | /* DRAM_WEB */ \ | |
163 | (1 << 16) | /* DRAM_BS[2:0] */ \ | |
164 | (0 << 15) | /* */ \ | |
165 | (0 << 12) | /* A12->out */ \ | |
166 | (0 << 11) | /* A11->RDQS */ \ | |
167 | (1 << 10) | /* A10->DQS# */ \ | |
168 | (7 << 7) | /* OCD program */ \ | |
169 | (0 << 6) | /* Rtt1 */ \ | |
170 | (0 << 3) | /* posted CAS# */ \ | |
171 | (1 << 2) | /* Rtt0 */ \ | |
172 | (0 << 1) | /* ODS (Output Drive Strength) */ \ | |
173 | (0 << 0) /* DLL */ \ | |
174 | ) | |
175 | ||
176 | /* | |
177 | * Backward compatible definitions, | |
a47a12be | 178 | * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c |
25671c86 | 179 | */ |
054197ba MS |
180 | #define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) |
181 | #define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) | |
182 | #define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR) | |
183 | #define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) | |
52568c36 WD |
184 | |
185 | /* DDR Priority Manager Configuration */ | |
186 | #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 | |
187 | #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 | |
188 | #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 | |
189 | #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC | |
190 | #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA | |
191 | #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 | |
192 | #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 | |
193 | #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 | |
194 | #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 | |
195 | #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 | |
196 | #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 | |
197 | #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 | |
198 | #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 | |
199 | #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa | |
200 | #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa | |
201 | #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 | |
202 | #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 | |
203 | #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 | |
204 | #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 | |
205 | #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 | |
206 | #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 | |
207 | #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 | |
208 | #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 | |
209 | ||
210 | /* | |
211 | * NOR FLASH on the Local Bus | |
212 | */ | |
213 | #define CONFIG_SYS_FLASH_CFI /* use the CFI code */ | |
214 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
215 | #define CONFIG_SYS_FLASH_BASE 0xF8000000 /* start of FLASH */ | |
216 | #define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max flash size */ | |
217 | ||
218 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
219 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
220 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
221 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max sectors */ | |
222 | ||
223 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
224 | ||
a6d6d46a WD |
225 | /* |
226 | * NAND FLASH support | |
227 | * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) | |
228 | */ | |
1f1f82f3 WD |
229 | #define CONFIG_CMD_NAND /* enable NAND support */ |
230 | #define CONFIG_JFFS2_NAND /* with JFFS2 on it */ | |
a6d6d46a WD |
231 | #define CONFIG_NAND_MPC5121_NFC |
232 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
a6d6d46a | 233 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
a6d6d46a | 234 | |
a6d6d46a WD |
235 | /* |
236 | * Configuration parameters for MPC5121 NAND driver | |
237 | */ | |
238 | #define CONFIG_FSL_NFC_WIDTH 1 | |
239 | #define CONFIG_FSL_NFC_WRITE_SIZE 2048 | |
240 | #define CONFIG_FSL_NFC_SPARE_SIZE 64 | |
241 | #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE | |
242 | ||
52568c36 WD |
243 | #define CONFIG_SYS_SRAM_BASE 0x30000000 |
244 | #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ | |
245 | ||
25671c86 WD |
246 | /* Make two SRAM regions contiguous */ |
247 | #define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \ | |
248 | CONFIG_SYS_SRAM_SIZE) | |
249 | #define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */ | |
676c6691 AG |
250 | #define CONFIG_SYS_CS6_START CONFIG_SYS_ARIA_SRAM_BASE |
251 | #define CONFIG_SYS_CS6_SIZE CONFIG_SYS_ARIA_SRAM_SIZE | |
52568c36 WD |
252 | |
253 | #define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \ | |
254 | CONFIG_SYS_ARIA_SRAM_SIZE) | |
255 | #define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */ | |
256 | ||
676c6691 AG |
257 | #define CONFIG_SYS_CS2_START CONFIG_SYS_ARIA_FPGA_BASE |
258 | #define CONFIG_SYS_CS2_SIZE CONFIG_SYS_ARIA_FPGA_SIZE | |
259 | ||
52568c36 WD |
260 | #define CONFIG_SYS_CS0_CFG 0x05059150 |
261 | #define CONFIG_SYS_CS2_CFG ( (5 << 24) | \ | |
262 | (5 << 16) | \ | |
263 | (1 << 15) | \ | |
264 | (0 << 14) | \ | |
265 | (0 << 13) | \ | |
266 | (1 << 12) | \ | |
267 | (0 << 10) | \ | |
268 | (3 << 8) | /* 32 bit */ \ | |
269 | (0 << 7) | \ | |
270 | (1 << 6) | \ | |
271 | (1 << 4) | \ | |
272 | (0 << 3) | \ | |
273 | (0 << 2) | \ | |
274 | (0 << 1) | \ | |
275 | (0 << 0) \ | |
276 | ) | |
277 | #define CONFIG_SYS_CS6_CFG 0x05059150 | |
278 | ||
279 | /* Use alternative CS timing for CS0 and CS2 */ | |
280 | #define CONFIG_SYS_CS_ALETIMING 0x00000005 | |
281 | ||
282 | /* Use SRAM for initial stack */ | |
283 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE | |
553f0982 | 284 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE |
52568c36 | 285 | |
553f0982 | 286 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
25ddd1fb | 287 | GENERATED_GBL_DATA_SIZE) |
52568c36 WD |
288 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
289 | ||
14d0a02a | 290 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
a6d6d46a | 291 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) |
52568c36 WD |
292 | |
293 | #ifdef CONFIG_FSL_DIU_FB | |
294 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) | |
295 | #else | |
296 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) | |
297 | #endif | |
298 | ||
299 | /* FPGA */ | |
300 | #define CONFIG_ARIA_FPGA 1 | |
301 | ||
302 | /* | |
303 | * Serial Port | |
304 | */ | |
305 | #define CONFIG_CONS_INDEX 1 | |
52568c36 WD |
306 | |
307 | /* | |
308 | * Serial console configuration | |
309 | */ | |
310 | #define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */ | |
bfb31279 | 311 | #define CONFIG_SYS_PSC3 |
52568c36 WD |
312 | #if CONFIG_PSC_CONSOLE != 3 |
313 | #error CONFIG_PSC_CONSOLE must be 3 | |
314 | #endif | |
315 | ||
316 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
317 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
318 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
319 | ||
320 | #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE | |
321 | #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR | |
322 | #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE | |
323 | #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR | |
324 | ||
325 | #define CONFIG_CMDLINE_EDITING 1 /* command line history */ | |
52568c36 WD |
326 | |
327 | /* | |
328 | * PCI | |
329 | */ | |
330 | #ifdef CONFIG_PCI | |
842033e6 | 331 | #define CONFIG_PCI_INDIRECT_BRIDGE |
52568c36 WD |
332 | |
333 | #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 | |
334 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
335 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
336 | #define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \ | |
337 | CONFIG_SYS_PCI_MEM_SIZE) | |
338 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
339 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
340 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
341 | #define CONFIG_SYS_PCI_IO_PHYS 0x84000000 | |
342 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ | |
343 | ||
344 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
345 | ||
346 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
347 | ||
348 | #endif | |
349 | ||
350 | /* I2C */ | |
351 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
52568c36 | 352 | #define CONFIG_I2C_MULTI_BUS |
52568c36 WD |
353 | |
354 | /* I2C speed and slave address */ | |
355 | #define CONFIG_SYS_I2C_SPEED 100000 | |
356 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
357 | #if 0 | |
358 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ | |
359 | #endif | |
360 | ||
361 | /* | |
362 | * IIM - IC Identification Module | |
363 | */ | |
83306927 | 364 | #undef CONFIG_FSL_IIM |
52568c36 WD |
365 | |
366 | /* | |
367 | * EEPROM configuration for Atmel AT24C32A-10TQ-2.7: | |
368 | * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode | |
369 | */ | |
370 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
371 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
372 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
373 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 | |
374 | ||
375 | /* | |
376 | * Ethernet configuration | |
377 | */ | |
378 | #define CONFIG_MPC512x_FEC 1 | |
52568c36 WD |
379 | #define CONFIG_PHY_ADDR 0x17 |
380 | #define CONFIG_MII 1 /* MII PHY management */ | |
381 | #define CONFIG_FEC_AN_TIMEOUT 1 | |
382 | #define CONFIG_HAS_ETH0 | |
383 | ||
384 | /* | |
385 | * Environment | |
386 | */ | |
387 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
388 | /* This has to be a multiple of the flash sector size */ | |
389 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ | |
390 | CONFIG_SYS_MONITOR_LEN) | |
391 | #define CONFIG_ENV_SIZE 0x2000 | |
392 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) */ | |
393 | ||
394 | /* Address and size of Redundant Environment Sector */ | |
395 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ | |
396 | CONFIG_ENV_SECT_SIZE) | |
397 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
398 | ||
399 | #define CONFIG_LOADS_ECHO 1 | |
400 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 | |
401 | ||
52568c36 WD |
402 | #define CONFIG_CMD_EEPROM |
403 | #undef CONFIG_CMD_FUSE | |
52568c36 | 404 | #undef CONFIG_CMD_IDE |
1f1f82f3 | 405 | #define CONFIG_CMD_JFFS2 |
52568c36 WD |
406 | #define CONFIG_CMD_REGINFO |
407 | ||
408 | #if defined(CONFIG_PCI) | |
409 | #define CONFIG_CMD_PCI | |
410 | #endif | |
411 | ||
1f1f82f3 | 412 | #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) |
52568c36 WD |
413 | #define CONFIG_DOS_PARTITION |
414 | #define CONFIG_MAC_PARTITION | |
415 | #define CONFIG_ISO_PARTITION | |
416 | #endif /* defined(CONFIG_CMD_IDE) */ | |
417 | ||
1f1f82f3 WD |
418 | /* |
419 | * Dynamic MTD partition support | |
420 | */ | |
421 | #define CONFIG_CMD_MTDPARTS | |
422 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
423 | #define CONFIG_FLASH_CFI_MTD | |
424 | #define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand" | |
425 | ||
426 | /* | |
427 | * NOR flash layout: | |
428 | * | |
429 | * F8000000 - FEAFFFFF 107 MiB User Data | |
430 | * FEB00000 - FFAFFFFF 16 MiB Root File System | |
431 | * FFB00000 - FFFEFFFF 4 MiB Linux Kernel | |
432 | * FFF00000 - FFFBFFFF 768 KiB U-Boot (up to 512 KiB) and 2 x * env | |
433 | * FFFC0000 - FFFFFFFF 256 KiB Device Tree | |
434 | * | |
435 | * NAND flash layout: one big partition | |
436 | */ | |
437 | #define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \ | |
438 | "16m(rootfs)," \ | |
439 | "4m(kernel)," \ | |
440 | "768k(u-boot)," \ | |
441 | "256k(dtb);" \ | |
442 | "mpc5121.nand:-(data)" | |
443 | ||
52568c36 WD |
444 | /* |
445 | * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. | |
446 | * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE | |
447 | * is set to 0xFFFF, watchdog timeouts after about 64s. For details | |
448 | * refer to chapter 36 of the MPC5121e Reference Manual. | |
449 | */ | |
450 | /* #define CONFIG_WATCHDOG */ /* enable watchdog */ | |
451 | #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF | |
452 | ||
453 | /* | |
454 | * Miscellaneous configurable options | |
455 | */ | |
456 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
457 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
52568c36 WD |
458 | |
459 | #ifdef CONFIG_CMD_KGDB | |
460 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
461 | #else | |
462 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
463 | #endif | |
464 | ||
465 | /* Print Buffer Size */ | |
466 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
467 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
468 | /* max number of command args */ | |
469 | #define CONFIG_SYS_MAXARGS 32 | |
470 | /* Boot Argument Buffer Size */ | |
471 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
472 | ||
52568c36 WD |
473 | /* |
474 | * For booting Linux, the board info and command line data | |
9f530d59 | 475 | * have to be in the first 256 MB of memory, since this is |
52568c36 WD |
476 | * the maximum mapped by the Linux kernel during initialization. |
477 | */ | |
9f530d59 | 478 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) |
52568c36 WD |
479 | |
480 | /* Cache Configuration */ | |
481 | #define CONFIG_SYS_DCACHE_SIZE 32768 | |
482 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
483 | #ifdef CONFIG_CMD_KGDB | |
484 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */ | |
485 | #endif | |
486 | ||
487 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
488 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
489 | HID0_ICE) | |
490 | #define CONFIG_SYS_HID2 HID2_HBE | |
491 | ||
492 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ | |
493 | ||
52568c36 WD |
494 | #ifdef CONFIG_CMD_KGDB |
495 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
52568c36 WD |
496 | #endif |
497 | ||
498 | /* | |
499 | * Environment Configuration | |
500 | */ | |
501 | #define CONFIG_ENV_OVERWRITE | |
502 | #define CONFIG_TIMESTAMP | |
503 | ||
504 | #define CONFIG_HOSTNAME aria | |
b3f44c21 | 505 | #define CONFIG_BOOTFILE "aria/uImage" |
8b3637c6 | 506 | #define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" |
52568c36 WD |
507 | |
508 | #define CONFIG_LOADADDR 400000 /* default load addr */ | |
509 | ||
52568c36 WD |
510 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
511 | ||
512 | #define CONFIG_BAUDRATE 115200 | |
513 | ||
514 | #define CONFIG_PREBOOT "echo;" \ | |
515 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ | |
516 | "echo" | |
517 | ||
518 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
519 | "u-boot_addr_r=200000\0" \ | |
520 | "kernel_addr_r=600000\0" \ | |
521 | "fdt_addr_r=880000\0" \ | |
522 | "ramdisk_addr_r=900000\0" \ | |
523 | "u-boot_addr=FFF00000\0" \ | |
1f1f82f3 WD |
524 | "kernel_addr=FFB00000\0" \ |
525 | "fdt_addr=FFFC0000\0" \ | |
526 | "ramdisk_addr=FEB00000\0" \ | |
52568c36 WD |
527 | "ramdiskfile=aria/uRamdisk\0" \ |
528 | "u-boot=aria/u-boot.bin\0" \ | |
529 | "fdtfile=aria/aria.dtb\0" \ | |
530 | "netdev=eth0\0" \ | |
531 | "consdev=ttyPSC0\0" \ | |
532 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
533 | "nfsroot=${serverip}:${rootpath}\0" \ | |
534 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
535 | "addip=setenv bootargs ${bootargs} " \ | |
536 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
537 | ":${hostname}:${netdev}:off panic=1\0" \ | |
538 | "addtty=setenv bootargs ${bootargs} " \ | |
539 | "console=${consdev},${baudrate}\0" \ | |
540 | "flash_nfs=run nfsargs addip addtty;" \ | |
541 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
542 | "flash_self=run ramargs addip addtty;" \ | |
543 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
544 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
545 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
546 | "run nfsargs addip addtty;" \ | |
547 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
548 | "net_self=tftp ${kernel_addr_r} ${bootfile};" \ | |
549 | "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ | |
550 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
551 | "run ramargs addip addtty;" \ | |
552 | "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ | |
553 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ | |
554 | "update=protect off ${u-boot_addr} +${filesize};" \ | |
555 | "era ${u-boot_addr} +${filesize};" \ | |
556 | "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ | |
557 | "upd=run load update\0" \ | |
558 | "" | |
559 | ||
560 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
561 | ||
52568c36 WD |
562 | #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 |
563 | ||
564 | #define OF_CPU "PowerPC,5121@0" | |
565 | #define OF_SOC_COMPAT "fsl,mpc5121-immr" | |
566 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
567 | #define OF_STDOUT_PATH "/soc@80000000/serial@11300" | |
568 | ||
569 | /*----------------------------------------------------------------------- | |
570 | * IDE/ATA stuff | |
571 | *----------------------------------------------------------------------- | |
572 | */ | |
573 | ||
574 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
575 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
576 | #undef CONFIG_IDE_LED /* LED for IDE not supported */ | |
577 | ||
578 | #define CONFIG_IDE_RESET /* reset for IDE supported */ | |
579 | #define CONFIG_IDE_PREINIT | |
580 | ||
581 | #define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */ | |
582 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* 1 drive per IDE bus */ | |
583 | ||
584 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
585 | #define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() | |
586 | ||
587 | /* Offset for data I/O RefMan MPC5121EE Table 28-10 */ | |
588 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) | |
589 | ||
590 | /* Offset for normal register accesses */ | |
591 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) | |
592 | ||
593 | /* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ | |
594 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) | |
595 | ||
596 | /* Interval between registers */ | |
597 | #define CONFIG_SYS_ATA_STRIDE 4 | |
598 | ||
599 | #define ATA_BASE_ADDR get_pata_base() | |
600 | ||
601 | /* | |
602 | * Control register bit definitions | |
603 | */ | |
604 | #define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 | |
605 | #define FSL_ATA_CTRL_ATA_RST_B 0x40000000 | |
606 | #define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 | |
607 | #define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 | |
608 | #define FSL_ATA_CTRL_DMA_PENDING 0x08000000 | |
609 | #define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 | |
610 | #define FSL_ATA_CTRL_DMA_WRITE 0x02000000 | |
611 | #define FSL_ATA_CTRL_IORDY_EN 0x01000000 | |
612 | ||
e5f53864 AG |
613 | /* Clocks in use */ |
614 | #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ | |
615 | CLOCK_SCCR1_LPC_EN | \ | |
616 | CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ | |
617 | CLOCK_SCCR1_PSCFIFO_EN | \ | |
618 | CLOCK_SCCR1_DDR_EN | \ | |
619 | CLOCK_SCCR1_FEC_EN | \ | |
620 | CLOCK_SCCR1_NFC_EN | \ | |
621 | CLOCK_SCCR1_PATA_EN | \ | |
622 | CLOCK_SCCR1_PCI_EN | \ | |
623 | CLOCK_SCCR1_TPR_EN) | |
624 | ||
625 | #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ | |
626 | CLOCK_SCCR2_SPDIF_EN | \ | |
627 | CLOCK_SCCR2_DIU_EN | \ | |
628 | CLOCK_SCCR2_I2C_EN) | |
629 | ||
52568c36 | 630 | #endif /* __CONFIG_H */ |