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ea66bc88 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * | |
6 | * 2004 (c) MontaVista Software, Inc. | |
7 | * | |
8 | * Configuation settings for the Intel Assabet board. | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
ea66bc88 WD |
32 | /* |
33 | * High Level Configuration Options | |
34 | * (easy to change) | |
35 | */ | |
36 | #define CONFIG_SA1110 1 /* This is an SA1100 CPU */ | |
37 | #define CONFIG_ASSABET 1 /* on an Intel Assabet Board */ | |
38 | ||
39 | #undef CONFIG_USE_IRQ | |
40 | ||
41 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
42 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
43 | #define CONFIG_INITRD_TAG 1 | |
44 | ||
45 | /* | |
46 | * Size of malloc() pool | |
47 | */ | |
6d0f6bcf JCPV |
48 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
49 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size rsrvd for initial data */ | |
ea66bc88 WD |
50 | |
51 | /* | |
52 | * Hardware drivers | |
53 | */ | |
54 | #define CONFIG_DRIVER_LAN91C96 /* we have an SMC9194 on-board */ | |
55 | #define CONFIG_LAN91C96_BASE 0x18000000 | |
56 | ||
57 | /* | |
58 | * select serial console configuration | |
59 | */ | |
60 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on Intel Assabet */ | |
61 | ||
62 | /* allow to overwrite serial and ethaddr */ | |
63 | #define CONFIG_ENV_OVERWRITE | |
64 | ||
65 | #define CONFIG_BAUDRATE 115200 | |
66 | ||
ea66bc88 | 67 | |
0b361c91 JL |
68 | /* |
69 | * Command line configuration. | |
70 | */ | |
71 | #include <config_cmd_default.h> | |
72 | ||
73 | #define CONFIG_CMD_DHCP | |
74 | ||
75 | ||
2fd90ce5 JL |
76 | /* |
77 | * BOOTP options | |
78 | */ | |
79 | #define CONFIG_BOOTP_SUBNETMASK | |
80 | #define CONFIG_BOOTP_GATEWAY | |
81 | #define CONFIG_BOOTP_HOSTNAME | |
82 | #define CONFIG_BOOTP_BOOTPATH | |
83 | ||
ea66bc88 WD |
84 | |
85 | #define CONFIG_BOOTDELAY 3 | |
86 | #define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp" | |
87 | #define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" | |
6d0f6bcf | 88 | #define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ |
ea66bc88 | 89 | |
0b361c91 | 90 | #if defined(CONFIG_CMD_KGDB) |
ea66bc88 WD |
91 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
92 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
93 | #endif | |
94 | ||
95 | /* | |
96 | * Miscellaneous configurable options | |
97 | */ | |
6d0f6bcf JCPV |
98 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
99 | #define CONFIG_SYS_PROMPT "Intel Assabet # " /* Monitor Command Prompt */ | |
100 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
101 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
102 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
103 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
ea66bc88 | 104 | |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */ |
106 | #define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ | |
ea66bc88 | 107 | |
6d0f6bcf | 108 | #undef CONFIG_SYS_CLKS_IN_HZ |
ea66bc88 | 109 | |
6d0f6bcf | 110 | #define CONFIG_SYS_LOAD_ADDR 0xc0000000 /* default load address */ |
ea66bc88 | 111 | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ |
113 | #define CONFIG_SYS_CPUSPEED 0x0a /* set core clock to 206MHz */ | |
ea66bc88 WD |
114 | |
115 | /* valid baudrates */ | |
6d0f6bcf | 116 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
ea66bc88 WD |
117 | |
118 | /*----------------------------------------------------------------------- | |
119 | * Stack sizes | |
120 | * | |
121 | * The stack sizes are set up in start.S using the settings below | |
122 | */ | |
123 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
124 | #ifdef CONFIG_USE_IRQ | |
125 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
126 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
127 | #endif | |
128 | ||
129 | /*----------------------------------------------------------------------- | |
130 | * Physical Memory Map | |
131 | */ | |
132 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ | |
133 | #define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ | |
134 | #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ | |
135 | ||
136 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
137 | #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ | |
138 | #define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ | |
139 | #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ | |
140 | ||
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
142 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ | |
ea66bc88 | 143 | |
6d0f6bcf JCPV |
144 | #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE |
145 | #define CONFIG_SYS_RAMSTART | |
ea66bc88 WD |
146 | #endif |
147 | ||
148 | /*----------------------------------------------------------------------- | |
149 | * FLASH and environment organization | |
150 | */ | |
151 | ||
6d0f6bcf JCPV |
152 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
153 | #define CONFIG_SYS_FLASH_SIZE PHYS_FLASH_SIZE | |
154 | #define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */ | |
00b1883a | 155 | #define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
157 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ | |
158 | #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ | |
159 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ | |
160 | #undef CONFIG_SYS_FLASH_PROTECTION | |
161 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
ea66bc88 | 162 | |
5a1aceb0 | 163 | #define CONFIG_ENV_IS_IN_FLASH 1 |
ea66bc88 | 164 | |
5a1aceb0 | 165 | #if defined(CONFIG_ENV_IS_IN_FLASH) |
0e8d1586 JCPV |
166 | #define CONFIG_ENV_IN_OWN_SECTOR 1 |
167 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) | |
168 | #define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE | |
169 | #define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE | |
ea66bc88 WD |
170 | #endif |
171 | ||
172 | #endif /* __CONFIG_H */ |