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9d79e575 WW |
1 | /* |
2 | * Configuration settings for the Sentec Cobra Board. | |
3 | * | |
4 | * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
9d79e575 WW |
7 | */ |
8 | ||
9 | /* | |
10 | * configuration for ASTRO "Urmel" board. | |
11 | * Originating from Cobra5272 configuration, messed up by | |
12 | * Wolfgang Wegner <w.wegner@astro-kom.de> | |
13 | * Please do not bother the original author with bug reports | |
14 | * concerning this file. | |
15 | */ | |
16 | ||
17 | #ifndef _CONFIG_ASTRO_MCF5373L_H | |
18 | #define _CONFIG_ASTRO_MCF5373L_H | |
19 | ||
51926d5e MV |
20 | #include <linux/stringify.h> |
21 | ||
9d79e575 WW |
22 | /* |
23 | * set the card type to actually compile for; either of | |
24 | * the possibilities listed below has to be used! | |
25 | */ | |
26 | #define CONFIG_ASTRO_V532 1 | |
27 | ||
28 | #if CONFIG_ASTRO_V532 | |
29 | #define ASTRO_ID 0xF8 | |
30 | #elif CONFIG_ASTRO_V512 | |
31 | #define ASTRO_ID 0xFA | |
32 | #elif CONFIG_ASTRO_TWIN7S2 | |
33 | #define ASTRO_ID 0xF9 | |
34 | #elif CONFIG_ASTRO_V912 | |
35 | #define ASTRO_ID 0xFC | |
36 | #elif CONFIG_ASTRO_COFDMDUOS2 | |
37 | #define ASTRO_ID 0xFB | |
38 | #else | |
39 | #error No card type defined! | |
40 | #endif | |
41 | ||
9d79e575 WW |
42 | #define CONFIG_ASTRO5373L /* define board type */ |
43 | ||
44 | /* Command line configuration */ | |
9d79e575 | 45 | /* |
d24f2d32 | 46 | * CONFIG_RAM defines if u-boot is loaded via BDM (or started from |
9d79e575 WW |
47 | * a different bootloader that has already performed RAM setup) or |
48 | * started directly from flash, which is the regular case for production | |
49 | * boards. | |
50 | */ | |
d24f2d32 | 51 | #ifdef CONFIG_RAM |
9d79e575 | 52 | #define CONFIG_MONITOR_IS_IN_RAM |
14d0a02a | 53 | #define CONFIG_SYS_TEXT_BASE 0x40020000 |
9d79e575 WW |
54 | #define ENABLE_JFFS 0 |
55 | #else | |
14d0a02a | 56 | #define CONFIG_SYS_TEXT_BASE 0x00000000 |
9d79e575 WW |
57 | #define ENABLE_JFFS 1 |
58 | #endif | |
59 | ||
60 | /* Define which commmands should be available at u-boot command prompt */ | |
61 | ||
62 | #define CONFIG_CMD_CACHE | |
63 | #define CONFIG_CMD_DATE | |
64 | #define CONFIG_CMD_ELF | |
9d79e575 | 65 | #define CONFIG_CMD_I2C |
9d79e575 WW |
66 | #if ENABLE_JFFS |
67 | #define CONFIG_CMD_JFFS2 | |
68 | #endif | |
69 | #define CONFIG_CMD_REGINFO | |
64e809af | 70 | #define CONFIG_CMD_FPGA_LOADMK |
9d79e575 WW |
71 | #define CONFIG_CMDLINE_EDITING |
72 | ||
73 | #define CONFIG_SYS_HUSH_PARSER | |
9d79e575 WW |
74 | |
75 | #define CONFIG_MCFRTC | |
76 | #undef RTC_DEBUG | |
77 | ||
78 | /* Timer */ | |
79 | #define CONFIG_MCFTMR | |
80 | #undef CONFIG_MCFPIT | |
81 | ||
82 | /* I2C */ | |
00f792e0 HS |
83 | #define CONFIG_SYS_I2C |
84 | #define CONFIG_SYS_I2C_FSL | |
85 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
86 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
87 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
9d79e575 WW |
88 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
89 | ||
90 | /* | |
91 | * Defines processor clock - important for correct timings concerning serial | |
92 | * interface etc. | |
9d79e575 WW |
93 | */ |
94 | ||
9d79e575 WW |
95 | #define CONFIG_SYS_CLK 80000000 |
96 | #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) | |
97 | #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ | |
98 | ||
99 | #define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 | |
100 | #define CONFIG_SYS_CORE_SRAM 0x80000000 | |
101 | ||
102 | #define CONFIG_SYS_UNIFY_CACHE | |
103 | ||
104 | /* | |
105 | * Define baudrate for UART1 (console output, tftp, ...) | |
106 | * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud | |
107 | * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected | |
108 | * in u-boot command interface | |
109 | */ | |
110 | ||
111 | #define CONFIG_BAUDRATE 115200 | |
9d79e575 WW |
112 | |
113 | #define CONFIG_MCFUART | |
114 | #define CONFIG_SYS_UART_PORT (2) | |
115 | #define CONFIG_SYS_UART2_ALT3_GPIO | |
116 | ||
117 | /* | |
118 | * Watchdog configuration; Watchdog is disabled for running from RAM | |
119 | * and set to highest possible value else. Beware there is no check | |
120 | * in the watchdog code to validate the timeout value set here! | |
121 | */ | |
122 | ||
123 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
124 | #define CONFIG_WATCHDOG | |
125 | #define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ | |
126 | #endif | |
127 | ||
128 | /* | |
129 | * Configuration for environment | |
130 | * Environment is located in the last sector of the flash | |
131 | */ | |
132 | ||
133 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
134 | #define CONFIG_ENV_OFFSET 0x1FF8000 | |
135 | #define CONFIG_ENV_SECT_SIZE 0x8000 | |
136 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
137 | #else | |
138 | /* | |
139 | * environment in RAM - This is used to use a single PC-based application | |
140 | * to load an image, load U-Boot, load an environment and then start U-Boot | |
141 | * to execute the commands from the environment. Feedback is done via setting | |
142 | * and reading memory locations. | |
143 | */ | |
144 | #define CONFIG_ENV_ADDR 0x40060000 | |
145 | #define CONFIG_ENV_SECT_SIZE 0x8000 | |
146 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
147 | #endif | |
148 | ||
149 | /* here we put our FPGA configuration... */ | |
150 | #define CONFIG_MISC_INIT_R 1 | |
151 | ||
152 | /* Define user parameters that have to be customized most likely */ | |
153 | ||
154 | /* AUTOBOOT settings - booting images automatically by u-boot after power on */ | |
155 | ||
156 | /* | |
157 | * used for autoboot, delay in seconds u-boot will wait before starting | |
158 | * defined (auto-)boot command, setting to -1 disables delay, setting to | |
159 | * 0 will too prevent access to u-boot command interface: u-boot then has | |
160 | * to be reflashed | |
161 | * beware - watchdog is not serviced during autoboot delay time! | |
162 | */ | |
163 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
164 | #define CONFIG_BOOTDELAY 1 | |
165 | #else | |
166 | #define CONFIG_BOOTDELAY 1 | |
167 | #endif | |
168 | ||
169 | /* | |
170 | * The following settings will be contained in the environment block ; if you | |
171 | * want to use a neutral environment all those settings can be manually set in | |
172 | * u-boot: 'set' command | |
173 | */ | |
174 | ||
9d79e575 WW |
175 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
176 | "loaderversion=11\0" \ | |
51926d5e | 177 | "card_id="__stringify(ASTRO_ID)"\0" \ |
9d79e575 WW |
178 | "alterafile=0\0" \ |
179 | "xilinxfile=0\0" \ | |
180 | "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\ | |
181 | "fpga load 0 0x41000000 $filesize\0" \ | |
182 | "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\ | |
183 | "fpga load 1 0x41000000 $filesize\0" \ | |
184 | "env_default=1\0" \ | |
185 | "env_check=if test $env_default -eq 1;"\ | |
186 | " then setenv env_default 0;saveenv;fi\0" | |
187 | ||
188 | /* | |
189 | * "update" is a non-standard command that has to be supplied | |
190 | * by external update.c; This is not included in mainline because | |
191 | * it needs non-blocking CFI routines. | |
192 | */ | |
193 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
194 | #define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */ | |
195 | #else | |
196 | #if CONFIG_ASTRO_V532 | |
197 | #define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ | |
198 | "run xilinxload&&run alteraload&&bootm 0x80000;"\ | |
199 | "update;reset" | |
200 | #else | |
201 | #define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ | |
202 | "run xilinxload&&bootm 0x80000;update;reset" | |
203 | #endif | |
204 | #endif | |
205 | ||
206 | /* default bootargs that are considered during boot */ | |
207 | #define CONFIG_BOOTARGS " console=ttyS2,115200 rootfstype=romfs"\ | |
208 | " loaderversion=$loaderversion" | |
209 | ||
9d79e575 WW |
210 | /* default RAM address for user programs */ |
211 | #define CONFIG_SYS_LOAD_ADDR 0x20000 | |
212 | ||
213 | #define CONFIG_SYS_LONGHELP | |
214 | ||
215 | #if (CONFIG_COMMANDS & CONFIG_CMD_KGDB) | |
216 | #define CONFIG_SYS_CBSIZE 1024 | |
217 | #else | |
218 | #define CONFIG_SYS_CBSIZE 256 | |
219 | #endif | |
220 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
221 | #define CONFIG_SYS_MAXARGS 16 | |
222 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
223 | ||
224 | #define CONFIG_FPGA_COUNT 1 | |
225 | #define CONFIG_FPGA | |
226 | #define CONFIG_FPGA_XILINX | |
227 | #define CONFIG_FPGA_SPARTAN3 | |
228 | #define CONFIG_FPGA_ALTERA | |
229 | #define CONFIG_FPGA_CYCLON2 | |
230 | #define CONFIG_SYS_FPGA_PROG_FEEDBACK | |
231 | #define CONFIG_SYS_FPGA_WAIT 1000 | |
232 | ||
233 | /* End of user parameters to be customized */ | |
234 | ||
235 | /* Defines memory range for test */ | |
236 | ||
237 | #define CONFIG_SYS_MEMTEST_START 0x40020000 | |
238 | #define CONFIG_SYS_MEMTEST_END 0x41ffffff | |
239 | ||
240 | /* | |
241 | * Low Level Configuration Settings | |
242 | * (address mappings, register initial values, etc.) | |
243 | * You should know what you are doing if you make changes here. | |
244 | */ | |
245 | ||
246 | /* Base register address */ | |
247 | ||
248 | #define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ | |
249 | ||
250 | /* System Conf. Reg. & System Protection Reg. */ | |
251 | ||
252 | #define CONFIG_SYS_SCR 0x0003; | |
253 | #define CONFIG_SYS_SPR 0xffff; | |
254 | ||
255 | /* | |
256 | * Definitions for initial stack pointer and data area (in internal SRAM) | |
257 | */ | |
258 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 | |
553f0982 | 259 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 |
9d79e575 | 260 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
553f0982 | 261 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
25ddd1fb | 262 | GENERATED_GBL_DATA_SIZE) |
9d79e575 WW |
263 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
264 | ||
265 | /* | |
266 | * Start addresses for the final memory configuration | |
267 | * (Set up by the startup code) | |
268 | * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 | |
269 | */ | |
270 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
271 | ||
272 | /* | |
273 | * Chipselect bank definitions | |
274 | * | |
275 | * CS0 - Flash 32MB (first 16MB) | |
276 | * CS1 - Flash 32MB (second half) | |
277 | * CS2 - FPGA | |
278 | * CS3 - FPGA | |
279 | * CS4 - unused | |
280 | * CS5 - unused | |
281 | */ | |
282 | #define CONFIG_SYS_CS0_BASE 0 | |
283 | #define CONFIG_SYS_CS0_MASK 0x00ff0001 | |
284 | #define CONFIG_SYS_CS0_CTRL 0x00001fc0 | |
285 | ||
286 | #define CONFIG_SYS_CS1_BASE 0x01000000 | |
287 | #define CONFIG_SYS_CS1_MASK 0x00ff0001 | |
288 | #define CONFIG_SYS_CS1_CTRL 0x00001fc0 | |
289 | ||
290 | #define CONFIG_SYS_CS2_BASE 0x20000000 | |
291 | #define CONFIG_SYS_CS2_MASK 0x00ff0001 | |
292 | #define CONFIG_SYS_CS2_CTRL 0x0000fec0 | |
293 | ||
294 | #define CONFIG_SYS_CS3_BASE 0x21000000 | |
295 | #define CONFIG_SYS_CS3_MASK 0x00ff0001 | |
296 | #define CONFIG_SYS_CS3_CTRL 0x0000fec0 | |
297 | ||
298 | #define CONFIG_SYS_FLASH_BASE 0x00000000 | |
299 | ||
300 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
14d0a02a | 301 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
9d79e575 WW |
302 | #else |
303 | /* This is mainly used during relocation in start.S */ | |
304 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) | |
305 | #endif | |
306 | /* Reserve 256 kB for Monitor */ | |
307 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
308 | ||
309 | #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) | |
310 | /* Reserve 128 kB for malloc() */ | |
311 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) | |
312 | ||
313 | /* | |
314 | * For booting Linux, the board info and command line data | |
315 | * have to be in the first 8 MB of memory, since this is | |
316 | * the maximum mapped by the Linux kernel during initialization ?? | |
317 | */ | |
318 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ | |
319 | (CONFIG_SYS_SDRAM_SIZE << 20)) | |
320 | ||
321 | /* FLASH organization */ | |
322 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
323 | #define CONFIG_SYS_MAX_FLASH_SECT 259 | |
324 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 | |
325 | ||
326 | #define CONFIG_SYS_FLASH_CFI 1 | |
327 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
328 | #define CONFIG_SYS_FLASH_SIZE 0x2000000 | |
329 | #define CONFIG_SYS_FLASH_PROTECTION 1 | |
330 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
331 | #define CONFIG_SYS_FLASH_CFI_NONBLOCK 1 | |
332 | ||
5296cb1d | 333 | #define LDS_BOARD_TEXT \ |
334 | . = DEFINED(env_offset) ? env_offset : .; \ | |
335 | common/env_embedded.o (.text*) | |
336 | ||
9d79e575 WW |
337 | #if ENABLE_JFFS |
338 | /* JFFS Partition offset set */ | |
339 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 | |
340 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
341 | /* 512k reserved for u-boot */ | |
342 | #define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40 | |
343 | #endif | |
344 | ||
345 | /* Cache Configuration */ | |
346 | #define CONFIG_SYS_CACHELINE_SIZE 16 | |
347 | ||
dd9f054e | 348 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 349 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 350 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 351 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
352 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) |
353 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
354 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
355 | CF_ACR_EN | CF_ACR_SM_ALL) | |
356 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ | |
357 | CF_CACR_DCM_P) | |
358 | ||
9d79e575 | 359 | #endif /* _CONFIG_ASTRO_MCF5373L_H */ |