[people/ms/u-boot.git] / include / configs / at91rm9200dk.h

/*
 * Rick Bronson <rick@efn.org>
 *
 * Configuation settings for the AT91RM9200DK board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
#define AT91C_MASTER_CLOCK	59904000	/* peripheral clock (AT91C_MASTER_CLOCK / 3) */
/* #define AT91C_MASTER_CLOCK	44928000 */	/* peripheral clock (AT91C_MASTER_CLOCK / 4) */

#define AT91_SLOW_CLOCK		32768	/* slow clock */

#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	*/
#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
#define USE_920T_MMU		1

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	1

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CFG_USE_MAIN_OSCILLATOR		1
/* flash */
#define MC_PUIA_VAL	0x00000000
#define MC_PUP_VAL	0x00000000
#define MC_PUER_VAL	0x00000000
#define MC_ASR_VAL	0x00000000
#define MC_AASR_VAL	0x00000000
#define EBI_CFGR_VAL	0x00000000
#define SMC2_CSR_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */

/* clocks */
#define PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */

/* sdram */
#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
#define PIOC_BSR_VAL	0x00000000
#define PIOC_PDR_VAL	0xFFFF0000
#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
#define SDRC_CR_VAL	0x2188c155 /* set up the SDRAM */
#define SDRAM		0x20000000 /* address of the SDRAM */
#define SDRAM1		0x20000080 /* address of the SDRAM */
#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
#define SDRC_MR_VAL	0x00000002 /* Precharge All */
#define SDRC_MR_VAL1	0x00000004 /* refresh */
#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
/*
 * Size of malloc() pool
 */
#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */

#define CONFIG_BAUDRATE 115200

/*
 * Hardware drivers
 */

/* define one of these to choose the DBGU, USART0  or USART1 as console */
#define CONFIG_DBGU
#undef CONFIG_USART0
#undef CONFIG_USART1

#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/

#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */

#define CONFIG_BOOTDELAY      3
/* #define CONFIG_ENV_OVERWRITE	1 */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_MII
#define CONFIG_CMD_DHCP

#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_MISC
#undef CONFIG_CMD_LOADS


#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
#define SECTORSIZE 512

#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3

#define NAND_ChipID_UNKNOWN	0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1

#define AT91_SMART_MEDIA_ALE (1 << 22)	/* our ALE is AD22 */
#define AT91_SMART_MEDIA_CLE (1 << 21)	/* our CLE is AD21 */

#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)

#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))

#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
/* the following are NOP's in our implementation */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)

#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#define PHYS_SDRAM_SIZE 0x2000000  /* 32 megs */

#define CFG_MEMTEST_START		PHYS_SDRAM
#define CFG_MEMTEST_END			CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144

#define CONFIG_DRIVER_ETHER
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_AT91C_USE_RMII

/* AC Characteristics */
/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
#define DATAFLASH_TCSS	(0xC << 16)
#define DATAFLASH_TCHS	(0x1 << 24)

#define CONFIG_HAS_DATAFLASH		1
#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
#define CFG_MAX_DATAFLASH_BANKS 	2
#define CFG_MAX_DATAFLASH_PAGES 	16384
#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */

#define PHYS_FLASH_1			0x10000000
#define PHYS_FLASH_SIZE			0x200000  /* 2 megs main flash */
#define CFG_FLASH_BASE			PHYS_FLASH_1
#define CFG_MAX_FLASH_BANKS		1
#define CFG_MAX_FLASH_SECT		256
#define CFG_FLASH_ERASE_TOUT		(2*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT		(2*CFG_HZ) /* Timeout for Flash Write */

#undef	CFG_ENV_IS_IN_DATAFLASH

#ifdef CFG_ENV_IS_IN_DATAFLASH
#define CFG_ENV_OFFSET			0x20000
#define CFG_ENV_ADDR			(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
#define CFG_ENV_SIZE			0x2000  /* 0x8000 */
#else
#define CFG_ENV_IS_IN_FLASH		1
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define CFG_ENV_ADDR			(PHYS_FLASH_1 + 0x60000)  /* after u-boot.bin */
#define CFG_ENV_SIZE			0x10000 /* sectors are 64K here */
#else
#define CFG_ENV_ADDR			(PHYS_FLASH_1 + 0xe000)  /* between boot.bin and u-boot.bin.gz */
#define CFG_ENV_SIZE			0x2000  /* 0x8000 */
#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
#endif	/* CFG_ENV_IS_IN_DATAFLASH */


#define CFG_LOAD_ADDR		0x21000000  /* default load address */

#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define CFG_BOOT_SIZE		0x00 /* 0 KBytes */
#define CFG_U_BOOT_BASE		PHYS_FLASH_1
#define CFG_U_BOOT_SIZE		0x60000 /* 384 KBytes */
#else
#define CFG_BOOT_SIZE		0x6000 /* 24 KBytes */
#define CFG_U_BOOT_BASE		(PHYS_FLASH_1 + 0x10000)
#define CFG_U_BOOT_SIZE		0x10000 /* 64 KBytes */
#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */

#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }

#define CFG_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
#define CFG_MAXARGS		16		/* max number of command args */
#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */

#ifndef __ASSEMBLY__
/*-----------------------------------------------------------------------
 * Board specific extension for bd_info
 *
 * This structure is embedded in the global bd_info (bd_t) structure
 * and can be used by the board specific code (eg board/...)
 */

struct bd_info_ext {
	/* helper variable for board environment handling
	 *
	 * env_crc_valid == 0    =>   uninitialised
	 * env_crc_valid  > 0    =>   environment crc in flash is valid
	 * env_crc_valid  < 0    =>   environment crc in flash is invalid
	 */
	int env_crc_valid;
};
#endif

#define CFG_HZ 1000
#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
					/* AT91C_TC_TIMER_DIV1_CLOCK */

#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */

#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif

#endif
Commit	Line	Data
dc7c9a1a WD	1	/*
	2	* Rick Bronson <rick@efn.org>
	3	*
	4	* Configuation settings for the AT91RM9200DK board.
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	/* ARM asynchronous clock */
8b07a110 WD	29	#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
	30	#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
	31	/* #define AT91C_MASTER_CLOCK 44928000 / / peripheral clock (AT91C_MASTER_CLOCK / 4) */
dc7c9a1a	32
d9df1f4e WD	33	#define AT91_SLOW_CLOCK 32768 /* slow clock */
d9df1f4e WD	34
a85f9f21 WD	35	#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
	36	#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
	37	#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
	38	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	39	#define USE_920T_MMU 1
	40
8b07a110	41	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
dc7c9a1a	42	#define CONFIG_SETUP_MEMORY_TAGS 1
8b07a110	43	#define CONFIG_INITRD_TAG 1
2abbe075	44
8aa1a2d1	45	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
ef2807c6 WD	46	#define CFG_USE_MAIN_OSCILLATOR 1
	47	/* flash */
	48	#define MC_PUIA_VAL 0x00000000
	49	#define MC_PUP_VAL 0x00000000
	50	#define MC_PUER_VAL 0x00000000
	51	#define MC_ASR_VAL 0x00000000
	52	#define MC_AASR_VAL 0x00000000
	53	#define EBI_CFGR_VAL 0x00000000
	54	#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
	55
	56	/* clocks */
	57	#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
	58	#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
	59	#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
	60
	61	/* sdram */
	62	#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
	63	#define PIOC_BSR_VAL 0x00000000
	64	#define PIOC_PDR_VAL 0xFFFF0000
	65	#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
	66	#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
	67	#define SDRAM 0x20000000 /* address of the SDRAM */
	68	#define SDRAM1 0x20000080 /* address of the SDRAM */
	69	#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
	70	#define SDRC_MR_VAL 0x00000002 /* Precharge All */
	71	#define SDRC_MR_VAL1 0x00000004 /* refresh */
	72	#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
	73	#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
	74	#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
8aa1a2d1	75	#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
dc7c9a1a WD	76	/*
	77	* Size of malloc() pool
	78	*/
	79	#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
a8c7c708 WD	80	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
a8c7c708 WD	81
dc7c9a1a	82	#define CONFIG_BAUDRATE 115200
a8c7c708	83
dc7c9a1a WD	84	/*
	85	* Hardware drivers
	86	*/
	87
9d5028c2	88	/* define one of these to choose the DBGU, USART0 or USART1 as console */
4734cb78	89	#define CONFIG_DBGU
9d5028c2	90	#undef CONFIG_USART0
4734cb78 WD	91	#undef CONFIG_USART1
4734cb78 WD	92
dc7c9a1a WD	93	#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
	94
	95	#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
	96
8bde7f77	97	#define CONFIG_BOOTDELAY 3
8b07a110	98	/* #define CONFIG_ENV_OVERWRITE 1 */
2abbe075	99
0b361c91	100
80ff4f99 JL	101	/*
	102	* BOOTP options
	103	*/
	104	#define CONFIG_BOOTP_BOOTFILESIZE
	105	#define CONFIG_BOOTP_BOOTPATH
	106	#define CONFIG_BOOTP_GATEWAY
	107	#define CONFIG_BOOTP_HOSTNAME
	108
	109
0b361c91 JL	110	/*
	111	* Command line configuration.
	112	*/
	113	#include <config_cmd_default.h>
	114
	115	#define CONFIG_CMD_MII
	116	#define CONFIG_CMD_DHCP
	117
	118	#undef CONFIG_CMD_BDI
	119	#undef CONFIG_CMD_IMI
	120	#undef CONFIG_CMD_AUTOSCRIPT
	121	#undef CONFIG_CMD_FPGA
	122	#undef CONFIG_CMD_MISC
	123	#undef CONFIG_CMD_LOADS
	124
dc7c9a1a WD	125
	126	#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
	127	#define SECTORSIZE 512
	128
	129	#define ADDR_COLUMN 1
	130	#define ADDR_PAGE 2
	131	#define ADDR_COLUMN_PAGE 3
	132
8b07a110	133	#define NAND_ChipID_UNKNOWN 0x00
dc7c9a1a WD	134	#define NAND_MAX_FLOORS 1
	135	#define NAND_MAX_CHIPS 1
	136
8b07a110 WD	137	#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
8b07a110 WD	138	#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
dc7c9a1a WD	139
	140	#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
	141	#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
	142
	143	#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
	144
	145	#define WRITE_NAND_COMMAND(d, adr) do{ (volatile __u8 )((unsigned long)adr \| AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
	146	#define WRITE_NAND_ADDRESS(d, adr) do{ (volatile __u8 )((unsigned long)adr \| AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
	147	#define WRITE_NAND(d, adr) do{ (volatile __u8 )((unsigned long)adr) = (__u8)d; } while(0)
	148	#define READ_NAND(adr) ((volatile unsigned char)((volatile __u8 )(unsigned long)adr))
	149	/* the following are NOP's in our implementation */
	150	#define NAND_CTL_CLRALE(nandptr)
	151	#define NAND_CTL_SETALE(nandptr)
	152	#define NAND_CTL_CLRCLE(nandptr)
	153	#define NAND_CTL_SETCLE(nandptr)
	154
	155	#define CONFIG_NR_DRAM_BANKS 1
	156	#define PHYS_SDRAM 0x20000000
	157	#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
	158
8b07a110 WD	159	#define CFG_MEMTEST_START PHYS_SDRAM
8b07a110 WD	160	#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
dc7c9a1a WD	161
dc7c9a1a WD	162	#define CONFIG_DRIVER_ETHER
8b07a110	163	#define CONFIG_NET_RETRY_COUNT 20
074cff0d	164	#define CONFIG_AT91C_USE_RMII
2abbe075	165
d4fc6012 PP	166	/* AC Characteristics */
	167	/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
	168	#define DATAFLASH_TCSS (0xC << 16)
	169	#define DATAFLASH_TCHS (0x1 << 24)
	170
8b07a110 WD	171	#define CONFIG_HAS_DATAFLASH 1
	172	#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
	173	#define CFG_MAX_DATAFLASH_BANKS 2
	174	#define CFG_MAX_DATAFLASH_PAGES 16384
2abbe075 WD	175	#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
2abbe075 WD	176	#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
dc7c9a1a	177
8b07a110 WD	178	#define PHYS_FLASH_1 0x10000000
	179	#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
	180	#define CFG_FLASH_BASE PHYS_FLASH_1
	181	#define CFG_MAX_FLASH_BANKS 1
	182	#define CFG_MAX_FLASH_SECT 256
	183	#define CFG_FLASH_ERASE_TOUT (2CFG_HZ) / Timeout for Flash Erase */
	184	#define CFG_FLASH_WRITE_TOUT (2CFG_HZ) / Timeout for Flash Write */
5779d8d9 WD	185
	186	#undef CFG_ENV_IS_IN_DATAFLASH
	187
	188	#ifdef CFG_ENV_IS_IN_DATAFLASH
8b07a110 WD	189	#define CFG_ENV_OFFSET 0x20000
	190	#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
	191	#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
5779d8d9	192	#else
8b07a110	193	#define CFG_ENV_IS_IN_FLASH 1
8aa1a2d1	194	#ifdef CONFIG_SKIP_LOWLEVEL_INIT
9d5028c2 WD	195	#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
	196	#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */
	197	#else
	198	#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
8b07a110	199	#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
8aa1a2d1	200	#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
400558b5	201	#endif /* CFG_ENV_IS_IN_DATAFLASH */
5779d8d9 WD	202
5779d8d9 WD	203
8b07a110	204	#define CFG_LOAD_ADDR 0x21000000 /* default load address */
dc7c9a1a	205
8aa1a2d1	206	#ifdef CONFIG_SKIP_LOWLEVEL_INIT
9d5028c2 WD	207	#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */
	208	#define CFG_U_BOOT_BASE PHYS_FLASH_1
	209	#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */
	210	#else
2abbe075	211	#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
8b07a110 WD	212	#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
8b07a110 WD	213	#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
8aa1a2d1	214	#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
2abbe075	215
8b07a110	216	#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
dc7c9a1a	217
8b07a110 WD	218	#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
	219	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	220	#define CFG_MAXARGS 16 /* max number of command args */
	221	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
dc7c9a1a WD	222
	223	#ifndef __ASSEMBLY__
	224	/*-----------------------------------------------------------------------
	225	* Board specific extension for bd_info
	226	*
	227	* This structure is embedded in the global bd_info (bd_t) structure
	228	* and can be used by the board specific code (eg board/...)
	229	*/
	230
8b07a110 WD	231	struct bd_info_ext {
	232	/* helper variable for board environment handling
	233	*
	234	* env_crc_valid == 0 => uninitialised
	235	* env_crc_valid > 0 => environment crc in flash is valid
	236	* env_crc_valid < 0 => environment crc in flash is invalid
	237	*/
	238	int env_crc_valid;
dc7c9a1a WD	239	};
	240	#endif
	241
9455b7f3 WD	242	#define CFG_HZ 1000
9455b7f3 WD	243	#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
8b07a110	244	/* AT91C_TC_TIMER_DIV1_CLOCK */
dc7c9a1a WD	245
	246	#define CONFIG_STACKSIZE (321024) / regular stack */
	247
	248	#ifdef CONFIG_USE_IRQ
	249	#error CONFIG_USE_IRQ not supported
	250	#endif
	251
	252	#endif