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dc7c9a1a WD |
1 | /* |
2 | * Rick Bronson <rick@efn.org> | |
3 | * | |
4 | * Configuation settings for the AT91RM9200DK board. | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #ifndef __CONFIG_H | |
26 | #define __CONFIG_H | |
27 | ||
28 | /* ARM asynchronous clock */ | |
29 | #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ | |
30 | #define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ | |
31 | ||
32 | #define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ | |
33 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
34 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
35 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
36 | #define CONFIG_INITRD_TAG 1 | |
37 | /* | |
38 | * Size of malloc() pool | |
39 | */ | |
40 | #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) | |
41 | #define CONFIG_BAUDRATE 115200 | |
42 | /* | |
43 | * Hardware drivers | |
44 | */ | |
45 | ||
46 | /* | |
47 | * select serial console configuration | |
48 | */ | |
49 | #define CONFIG_SERIAL3 1 /* we use SERIAL 3 */ | |
50 | ||
51 | #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ | |
52 | ||
53 | #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ | |
54 | ||
55 | #define CONFIG_COMMANDS \ | |
56 | (CONFIG_CMD_DFL | \ | |
57 | CFG_CMD_DHCP | \ | |
58 | CFG_CMD_NAND ) | |
59 | /* CFG_CMD_EEPROM | \ might consider these | |
60 | CFG_CMD_I2C | \ | |
61 | CFG_CMD_USB | \ | |
62 | CFG_CMD_MII | \ | |
63 | CFG_CMD_SDRAM | \ */ | |
64 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
65 | #include <cmd_confdefs.h> | |
66 | ||
67 | #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ | |
68 | #define SECTORSIZE 512 | |
69 | ||
70 | #define ADDR_COLUMN 1 | |
71 | #define ADDR_PAGE 2 | |
72 | #define ADDR_COLUMN_PAGE 3 | |
73 | ||
74 | #define NAND_ChipID_UNKNOWN 0x00 | |
75 | #define NAND_MAX_FLOORS 1 | |
76 | #define NAND_MAX_CHIPS 1 | |
77 | ||
78 | #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ | |
79 | #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ | |
80 | ||
81 | #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) | |
82 | #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) | |
83 | ||
84 | #define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) | |
85 | ||
86 | #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) | |
87 | #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) | |
88 | #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) | |
89 | #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) | |
90 | /* the following are NOP's in our implementation */ | |
91 | #define NAND_CTL_CLRALE(nandptr) | |
92 | #define NAND_CTL_SETALE(nandptr) | |
93 | #define NAND_CTL_CLRCLE(nandptr) | |
94 | #define NAND_CTL_SETCLE(nandptr) | |
95 | ||
96 | #define CONFIG_NR_DRAM_BANKS 1 | |
97 | #define PHYS_SDRAM 0x20000000 | |
98 | #define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ | |
99 | ||
100 | #define CFG_MEMTEST_START PHYS_SDRAM | |
101 | #define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 | |
102 | ||
103 | #define CONFIG_DRIVER_ETHER | |
104 | ||
105 | #define PHYS_FLASH_1 0x10000000 | |
106 | #define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */ | |
107 | #define CFG_FLASH_BASE PHYS_FLASH_1 | |
108 | #define CFG_MAX_FLASH_BANKS 1 | |
109 | #define CFG_MAX_FLASH_SECT 40 | |
110 | #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ | |
111 | #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ | |
112 | #define CFG_ENV_IS_IN_FLASH 1 | |
113 | #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) | |
114 | #define CFG_ENV_SIZE 0x2000 | |
115 | #define CFG_LOAD_ADDR 0x21000000 /* default load address */ | |
116 | ||
117 | #define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } | |
118 | ||
119 | #define CFG_PROMPT "Uboot> " /* Monitor Command Prompt */ | |
120 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
121 | #define CFG_MAXARGS 16 /* max number of command args */ | |
122 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
123 | ||
124 | #ifndef __ASSEMBLY__ | |
125 | /*----------------------------------------------------------------------- | |
126 | * Board specific extension for bd_info | |
127 | * | |
128 | * This structure is embedded in the global bd_info (bd_t) structure | |
129 | * and can be used by the board specific code (eg board/...) | |
130 | */ | |
131 | ||
132 | struct bd_info_ext | |
133 | { | |
134 | /* helper variable for board environment handling | |
135 | * | |
136 | * env_crc_valid == 0 => uninitialised | |
137 | * env_crc_valid > 0 => environment crc in flash is valid | |
138 | * env_crc_valid < 0 => environment crc in flash is invalid | |
139 | */ | |
140 | int env_crc_valid; | |
141 | }; | |
142 | #endif | |
143 | ||
144 | #define CFG_HZ AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to | |
145 | AT91C_TC_TIMER_DIV1_CLOCK */ | |
146 | ||
147 | #define CONFIG_STACKSIZE (32*1024) /* regular stack */ | |
148 | ||
149 | #ifdef CONFIG_USE_IRQ | |
150 | #error CONFIG_USE_IRQ not supported | |
151 | #endif | |
152 | ||
153 | #endif |