]>
Commit | Line | Data |
---|---|---|
cb82a532 | 1 | /* |
99fa97e9 AB |
2 | * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com> |
3 | * | |
4 | * based on previous work by | |
5 | * | |
cb82a532 US |
6 | * Ulf Samuelsson <ulf@atmel.com> |
7 | * Rick Bronson <rick@efn.org> | |
8 | * | |
9 | * Configuration settings for the AT91RM9200EK board. | |
10 | * | |
1a459660 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
cb82a532 US |
12 | */ |
13 | ||
99fa97e9 AB |
14 | #ifndef __AT91RM9200EK_CONFIG_H__ |
15 | #define __AT91RM9200EK_CONFIG_H__ | |
cb82a532 | 16 | |
99fa97e9 | 17 | #include <asm/sizes.h> |
425de62d | 18 | |
3a4ff8b3 AB |
19 | /* |
20 | * set some initial configurations depending on configure target | |
21 | * | |
22 | * at91rm9200ek_config -> boot from 0x0 in NOR Flash at CS0 | |
23 | * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel | |
24 | * initialisation was done by some preloader | |
25 | */ | |
26 | #ifdef CONFIG_RAMBOOT | |
27 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
28 | #define CONFIG_SYS_TEXT_BASE 0x20100000 | |
29 | #else | |
30 | #define CONFIG_SYS_TEXT_BASE 0x10000000 | |
31 | #endif | |
32 | ||
cb82a532 | 33 | /* |
99fa97e9 AB |
34 | * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz |
35 | * AT91C_MAIN_CLOCK is the frequency of PLLA output | |
36 | * AT91C_MASTER_CLOCK is the peripherial clock | |
37 | * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely | |
38 | * set in arch/arm/cpu/arm920t/at91/timer.c) | |
39 | * CONFIG_SYS_HZ is the tick rate for timer tc0 | |
cb82a532 | 40 | */ |
99fa97e9 | 41 | #define AT91C_XTAL_CLOCK 18432000 |
6a372e94 | 42 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
99fa97e9 AB |
43 | #define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) |
44 | #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 ) | |
45 | #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) | |
46 | #define CONFIG_SYS_HZ 1000 | |
cb82a532 | 47 | |
99fa97e9 | 48 | /* CPU configuration */ |
99fa97e9 AB |
49 | #define CONFIG_AT91RM9200 |
50 | #define CONFIG_AT91RM9200EK | |
51 | #define CONFIG_CPUAT91 | |
52 | #define USE_920T_MMU | |
cb82a532 | 53 | |
6a372e94 AB |
54 | #include <asm/hardware.h> /* needed for port definitions */ |
55 | ||
99fa97e9 AB |
56 | #define CONFIG_CMDLINE_TAG |
57 | #define CONFIG_SETUP_MEMORY_TAGS | |
58 | #define CONFIG_INITRD_TAG | |
59 | ||
3432a93b AB |
60 | #define CONFIG_BOARD_EARLY_INIT_F |
61 | ||
f9129fe3 | 62 | #define CONFIG_CMD_BOOTZ |
36873e7d NF |
63 | #define CONFIG_OF_LIBFDT |
64 | ||
99fa97e9 AB |
65 | /* |
66 | * Memory Configuration | |
67 | */ | |
68 | #define CONFIG_NR_DRAM_BANKS 1 | |
69 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 | |
70 | #define CONFIG_SYS_SDRAM_SIZE SZ_32M | |
cb82a532 | 71 | |
99fa97e9 AB |
72 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
73 | #define CONFIG_SYS_MEMTEST_END \ | |
74 | (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K) | |
cb82a532 US |
75 | |
76 | /* | |
77 | * LowLevel Init | |
78 | */ | |
79 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT | |
99fa97e9 | 80 | #define CONFIG_SYS_USE_MAIN_OSCILLATOR |
cb82a532 | 81 | /* flash */ |
cb82a532 US |
82 | #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 |
83 | #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ | |
84 | ||
85 | /* clocks */ | |
86 | #define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ | |
87 | #define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ | |
88 | /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ | |
89 | #define CONFIG_SYS_MCKR_VAL 0x00000202 | |
90 | ||
91 | /* sdram */ | |
92 | #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ | |
93 | #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 | |
94 | #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 | |
95 | #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ | |
96 | #define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ | |
99fa97e9 | 97 | #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */ |
066df1a5 | 98 | #define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80) |
cb82a532 US |
99 | #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ |
100 | #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ | |
101 | #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ | |
102 | #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ | |
103 | #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ | |
104 | #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ | |
cb82a532 US |
105 | #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
106 | ||
cb82a532 US |
107 | /* |
108 | * Hardware drivers | |
109 | */ | |
cb82a532 | 110 | /* |
99fa97e9 AB |
111 | * Choose a USART for serial console |
112 | * CONFIG_DBGU is DBGU unit on J10 | |
113 | * CONFIG_USART1 is USART1 on J14 | |
cb82a532 | 114 | */ |
3432a93b AB |
115 | #define CONFIG_ATMEL_USART |
116 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU | |
117 | #define CONFIG_USART_ID 0/* ignored in arm */ | |
cb82a532 | 118 | |
cb82a532 US |
119 | #define CONFIG_BAUDRATE 115200 |
120 | ||
121 | /* | |
122 | * Command line configuration. | |
123 | */ | |
124 | #include <config_cmd_default.h> | |
125 | ||
126 | #define CONFIG_CMD_DHCP | |
127 | #define CONFIG_CMD_FAT | |
128 | #define CONFIG_CMD_MII | |
129 | #define CONFIG_CMD_PING | |
3b83522b | 130 | #define CONFIG_CMD_USB |
cb82a532 | 131 | #undef CONFIG_CMD_FPGA |
cb82a532 US |
132 | |
133 | /* | |
134 | * Network Driver Setting | |
135 | */ | |
99fa97e9 AB |
136 | #define CONFIG_DRIVER_AT91EMAC |
137 | #define CONFIG_SYS_RX_ETH_BUFFER 16 | |
138 | #define CONFIG_RMII | |
139 | #define CONFIG_MII | |
cb82a532 US |
140 | |
141 | /* | |
142 | * NOR Flash | |
143 | */ | |
99fa97e9 AB |
144 | #define CONFIG_FLASH_CFI_DRIVER |
145 | #define CONFIG_SYS_FLASH_CFI | |
146 | #define CONFIG_SYS_FLASH_BASE 0x10000000 | |
147 | #define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE | |
148 | #define PHYS_FLASH_SIZE SZ_8M | |
149 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
150 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
cb82a532 US |
151 | #define CONFIG_SYS_FLASH_PROTECTION |
152 | ||
3b83522b AB |
153 | /* |
154 | * USB Config | |
155 | */ | |
156 | #define CONFIG_USB_ATMEL 1 | |
157 | #define CONFIG_USB_OHCI_NEW 1 | |
158 | #define CONFIG_USB_KEYBOARD 1 | |
159 | #define CONFIG_USB_STORAGE 1 | |
160 | #define CONFIG_DOS_PARTITION 1 | |
161 | ||
162 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | |
80733994 | 163 | #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_USB_HOST_BASE |
3b83522b AB |
164 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" |
165 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
166 | ||
cb82a532 US |
167 | /* |
168 | * Environment Settings | |
169 | */ | |
99fa97e9 | 170 | #define CONFIG_ENV_IS_IN_FLASH |
cb82a532 | 171 | |
cb82a532 US |
172 | /* |
173 | * after u-boot.bin | |
174 | */ | |
175 | #define CONFIG_ENV_ADDR \ | |
176 | (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) | |
99fa97e9 | 177 | #define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */ |
cb82a532 US |
178 | /* The following #defines are needed to get flash environment right */ |
179 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
99fa97e9 | 180 | #define CONFIG_SYS_MONITOR_LEN SZ_256K |
cb82a532 US |
181 | |
182 | /* | |
183 | * Boot option | |
184 | */ | |
185 | #define CONFIG_BOOTDELAY 3 | |
186 | ||
99fa97e9 AB |
187 | /* default load address */ |
188 | #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M | |
189 | #define CONFIG_ENV_OVERWRITE | |
cb82a532 US |
190 | |
191 | /* | |
192 | * Shell Settings | |
193 | */ | |
99fa97e9 AB |
194 | #define CONFIG_CMDLINE_EDITING |
195 | #define CONFIG_SYS_LONGHELP | |
196 | #define CONFIG_AUTO_COMPLETE | |
197 | #define CONFIG_SYS_HUSH_PARSER | |
cb82a532 | 198 | #define CONFIG_SYS_PROMPT "U-Boot> " |
cb82a532 US |
199 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
200 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
201 | /* Print Buffer Size */ | |
202 | #define CONFIG_SYS_PBSIZE \ | |
203 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
204 | ||
cb82a532 US |
205 | /* |
206 | * Size of malloc() pool | |
207 | */ | |
99fa97e9 AB |
208 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \ |
209 | SZ_4K) | |
cb82a532 | 210 | |
99fa97e9 | 211 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ |
25ddd1fb | 212 | - GENERATED_GBL_DATA_SIZE) |
99fa97e9 | 213 | |
99fa97e9 | 214 | #endif /* __AT91RM9200EK_CONFIG_H__ */ |