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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
d99a8ff6 SP |
2 | /* |
3 | * (C) Copyright 2007-2008 | |
c9e798d3 | 4 | * Stelian Pop <stelian@popies.net> |
d99a8ff6 SP |
5 | * Lead Tech Design <www.leadtechdesign.com> |
6 | * | |
7 | * Configuation settings for the AT91SAM9261EK board. | |
d99a8ff6 SP |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | /* ARM asynchronous clock */ | |
f7aea46d | 14 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
7c966a8b | 15 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ |
d99a8ff6 | 16 | |
f7aea46d XH |
17 | #ifdef CONFIG_AT91SAM9G10 |
18 | #define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/ | |
5ccc2d99 | 19 | #else |
f7aea46d | 20 | #define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK*/ |
5ccc2d99 | 21 | #endif |
f7aea46d XH |
22 | |
23 | #include <asm/hardware.h> | |
24 | ||
f7aea46d XH |
25 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
26 | #define CONFIG_SETUP_MEMORY_TAGS | |
27 | #define CONFIG_INITRD_TAG | |
d99a8ff6 SP |
28 | |
29 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
d99a8ff6 | 30 | |
f7aea46d | 31 | #define CONFIG_ATMEL_LEGACY |
f7aea46d | 32 | |
d99a8ff6 SP |
33 | /* |
34 | * Hardware drivers | |
35 | */ | |
f7aea46d | 36 | |
820f2a95 | 37 | /* LCD */ |
820f2a95 | 38 | #define LCD_BPP LCD_COLOR8 |
f7aea46d | 39 | #define CONFIG_LCD_LOGO |
820f2a95 | 40 | #undef LCD_TEST_PATTERN |
f7aea46d XH |
41 | #define CONFIG_LCD_INFO |
42 | #define CONFIG_LCD_INFO_BELOW_LOGO | |
f7aea46d | 43 | #define CONFIG_ATMEL_LCD |
5ccc2d99 | 44 | #ifdef CONFIG_AT91SAM9261EK |
f7aea46d | 45 | #define CONFIG_ATMEL_LCD_BGR555 |
5ccc2d99 | 46 | #endif |
f7aea46d | 47 | |
d99a8ff6 SP |
48 | /* |
49 | * BOOTP options | |
50 | */ | |
f7aea46d | 51 | #define CONFIG_BOOTP_BOOTFILESIZE |
d99a8ff6 | 52 | |
d99a8ff6 | 53 | /* SDRAM */ |
f7aea46d XH |
54 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
55 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 | |
56 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
324873e7 | 57 | (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
d99a8ff6 SP |
58 | |
59 | /* NAND flash */ | |
74c076d6 | 60 | #ifdef CONFIG_CMD_NAND |
6d0f6bcf JCPV |
61 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
62 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
f7aea46d | 63 | #define CONFIG_SYS_NAND_DBW_8 |
74c076d6 JCPV |
64 | /* our ALE is AD22 */ |
65 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) | |
66 | /* our CLE is AD21 */ | |
67 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) | |
68 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 | |
69 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15 | |
2eb99ca8 | 70 | |
74c076d6 | 71 | #endif |
d99a8ff6 | 72 | |
d99a8ff6 | 73 | /* Ethernet */ |
f7aea46d | 74 | #define CONFIG_DRIVER_DM9000 |
d99a8ff6 SP |
75 | #define CONFIG_DM9000_BASE 0x30000000 |
76 | #define DM9000_IO CONFIG_DM9000_BASE | |
77 | #define DM9000_DATA (CONFIG_DM9000_BASE + 4) | |
f7aea46d XH |
78 | #define CONFIG_DM9000_USE_16BIT |
79 | #define CONFIG_DM9000_NO_SROM | |
d99a8ff6 | 80 | #define CONFIG_NET_RETRY_COUNT 20 |
f7aea46d | 81 | #define CONFIG_RESET_PHY_R |
d99a8ff6 SP |
82 | |
83 | /* USB */ | |
2b7178af | 84 | #define CONFIG_USB_ATMEL |
dcd2f1a0 | 85 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
f7aea46d | 86 | #define CONFIG_USB_OHCI_NEW |
f7aea46d | 87 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
6d0f6bcf | 88 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ |
5ccc2d99 SG |
89 | #ifdef CONFIG_AT91SAM9G10EK |
90 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10" | |
91 | #else | |
6d0f6bcf | 92 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" |
5ccc2d99 | 93 | #endif |
6d0f6bcf | 94 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
d99a8ff6 | 95 | |
6d0f6bcf | 96 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
d99a8ff6 | 97 | |
6d0f6bcf | 98 | #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 |
d99a8ff6 SP |
99 | |
100 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ | |
324873e7 WY |
101 | #define CONFIG_BOOTCOMMAND "sf probe 0; " \ |
102 | "sf read 0x22000000 0x84000 0x294000; " \ | |
103 | "bootm 0x22000000" | |
d99a8ff6 | 104 | |
89a7a87f NF |
105 | #elif CONFIG_SYS_USE_DATAFLASH_CS3 |
106 | ||
107 | /* bootstrap + u-boot + env + linux in dataflash on CS3 */ | |
324873e7 WY |
108 | #define CONFIG_BOOTCOMMAND "sf probe 0:3; " \ |
109 | "sf read 0x22000000 0x84000 0x294000; " \ | |
110 | "bootm 0x22000000" | |
89a7a87f | 111 | |
6d0f6bcf | 112 | #else /* CONFIG_SYS_USE_NANDFLASH */ |
d99a8ff6 SP |
113 | |
114 | /* bootstrap + u-boot + env + linux in nandflash */ | |
0c58cfa9 | 115 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" |
d99a8ff6 SP |
116 | #endif |
117 | ||
d99a8ff6 SP |
118 | /* |
119 | * Size of malloc() pool | |
120 | */ | |
6d0f6bcf | 121 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) |
d99a8ff6 | 122 | |
d99a8ff6 | 123 | #endif |