[thirdparty/u-boot.git] / include / configs / at91sam9263ek.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * Configuation settings for the AT91SAM9263EK board.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <linux/stringify.h>

/*
 * SoC must be defined first, before hardware.h is included.
 * In this case SoC is defined in boards.cfg.
 */
#include <asm/hardware.h>

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	1

#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
#else
#define CONFIG_SYS_USE_NORFLASH
#endif

/*
 * Hardware drivers
 */
#define CONFIG_ATMEL_LEGACY

/* LCD */
#define LCD_BPP				LCD_COLOR8
#define CONFIG_LCD_LOGO			1
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO			1
#define CONFIG_LCD_INFO_BELOW_LOGO	1
#define CONFIG_ATMEL_LCD		1
#define CONFIG_ATMEL_LCD_BGR555		1

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE	1

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE		0x04000000

#define CONFIG_SYS_INIT_SP_ADDR \
	(ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)

/* NOR flash, if populated */
#ifdef CONFIG_SYS_USE_NORFLASH
#define PHYS_FLASH_1				0x10000000
#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT		256
#define CONFIG_SYS_MAX_FLASH_BANKS		1

#define CONFIG_SYS_MONITOR_SEC	1:0-3
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN	(256 << 10)

/* Address and size of Primary Environment Sector */

#define CONFIG_EXTRA_ENV_SETTINGS	\
	"monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
	"update=" \
		"protect off ${monitor_base} +${filesize};" \
		"erase ${monitor_base} +${filesize};" \
		"cp.b ${fileaddr} ${monitor_base} ${filesize};" \
		"protect on ${monitor_base} +${filesize}\0"

#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define MASTER_PLL_MUL		171
#define MASTER_PLL_DIV		14
#define MASTER_PLL_OUT		3

/* clocks */
#define CONFIG_SYS_MOR_VAL						\
		(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
#define CONFIG_SYS_PLLAR_VAL					\
	(AT91_PMC_PLLAR_29 |					\
	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | 		\
	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))

/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR1_VAL		\
	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
	 AT91_PMC_MCKR_MDIV_2)

/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR2_VAL		\
	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | 	\
	AT91_PMC_MCKR_MDIV_2)

/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
#define CONFIG_SYS_MATRIX_EBICSA_VAL					\
	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
	 AT91_MATRIX_CSA_EBI_CS1A)

/* SDRAM */
/* SDRAMC_MR Mode register */
#define CONFIG_SYS_SDRC_MR_VAL1		0
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1		0x13C
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL							\
		(AT91_SDRAMC_NC_9 |						\
		 AT91_SDRAMC_NR_13 |						\
		 AT91_SDRAMC_NB_4 |						\
		 AT91_SDRAMC_CAS_3 |						\
		 AT91_SDRAMC_DBW_32 |						\
		 (1 <<  8) |		/* Write Recovery Delay */		\
		 (7 << 12) |		/* Row Cycle Delay */			\
		 (2 << 16) |		/* Row Precharge Delay */		\
		 (2 << 20) |		/* Row to Column Delay */		\
		 (5 << 24) |		/* Active to Precharge Delay */		\
		 (1 << 28))		/* Exit Self Refresh to Active Delay */

/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */

/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL				\
	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL				\
	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
#define CONFIG_SYS_SMC0_MODE0_VAL				\
	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
	 AT91_SMC_MODE_DBW_16 |					\
	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))

/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL			\
		(AT91_RSTC_KEY |		\
		AT91_RSTC_MR_URSTEN |		\
		AT91_RSTC_MR_ERSTL(15))

/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL				\
		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
		 AT91_WDT_MR_WDV(0xfff) |			\
		 AT91_WDT_MR_WDDIS |				\
		 AT91_WDT_MR_WDD(0xfff))

#endif
#include <linux/stringify.h>
#endif

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8			1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
#endif

/* Ethernet */
#define CONFIG_RESET_PHY_R		1
#define CONFIG_AT91_WANTS_COMMON_PHY

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW		1
#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2

#ifdef CONFIG_SYS_USE_DATAFLASH

/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
				"sf read 0x22000000 0x84000 0x294000; " \
				"bootm 0x22000000"

#elif CONFIG_SYS_USE_NANDFLASH

/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
#endif

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
8e429b3e SP	2	/*
8e429b3e SP	3	* (C) Copyright 2007-2008
c9e798d3	4	* Stelian Pop <stelian@popies.net>
8e429b3e SP	5	* Lead Tech Design <www.leadtechdesign.com>
	6	*
	7	* Configuation settings for the AT91SAM9263EK board.
8e429b3e SP	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
1af3c7f4 SG	13	#include <linux/stringify.h>
1af3c7f4 SG	14
cd46b0f2 XH	15	/*
	16	* SoC must be defined first, before hardware.h is included.
	17	* In this case SoC is defined in boards.cfg.
	18	*/
	19	#include <asm/hardware.h>
	20
8e429b3e	21	/* ARM asynchronous clock */
cd46b0f2 XH	22	#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
cd46b0f2 XH	23	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
cd46b0f2	24
8e429b3e SP	25	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	26	#define CONFIG_SETUP_MEMORY_TAGS 1
	27	#define CONFIG_INITRD_TAG 1
	28
1b3b7c64	29	#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
cd46b0f2 XH	30	#else
cd46b0f2 XH	31	#define CONFIG_SYS_USE_NORFLASH
1b3b7c64	32	#endif
8e429b3e SP	33
	34	/*
	35	* Hardware drivers
	36	*/
cd46b0f2	37	#define CONFIG_ATMEL_LEGACY
8e429b3e	38
56a2479c	39	/* LCD */
56a2479c SP	40	#define LCD_BPP LCD_COLOR8
	41	#define CONFIG_LCD_LOGO 1
	42	#undef LCD_TEST_PATTERN
	43	#define CONFIG_LCD_INFO 1
	44	#define CONFIG_LCD_INFO_BELOW_LOGO 1
56a2479c SP	45	#define CONFIG_ATMEL_LCD 1
56a2479c SP	46	#define CONFIG_ATMEL_LCD_BGR555 1
56a2479c	47
8e429b3e SP	48	/*
	49	* BOOTP options
	50	*/
	51	#define CONFIG_BOOTP_BOOTFILESIZE 1
8e429b3e	52
8e429b3e	53	/* SDRAM */
cd46b0f2 XH	54	#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
	55	#define CONFIG_SYS_SDRAM_SIZE 0x04000000
	56
	57	#define CONFIG_SYS_INIT_SP_ADDR \
0b8908f9	58	(ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
8e429b3e	59
8e429b3e	60	/* NOR flash, if populated */
1b3b7c64	61	#ifdef CONFIG_SYS_USE_NORFLASH
1b3b7c64	62	#define PHYS_FLASH_1 0x10000000
6d0f6bcf JCPV	63	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	64	#define CONFIG_SYS_MAX_FLASH_SECT 256
	65	#define CONFIG_SYS_MAX_FLASH_BANKS 1
1b3b7c64 JCPV	66
	67	#define CONFIG_SYS_MONITOR_SEC 1:0-3
	68	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	69	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
1b3b7c64 JCPV	70
1b3b7c64 JCPV	71	/* Address and size of Primary Environment Sector */
1b3b7c64	72
1b3b7c64	73	#define CONFIG_EXTRA_ENV_SETTINGS \
93ea89f0	74	"monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
1b3b7c64 JCPV	75	"update=" \
	76	"protect off ${monitor_base} +${filesize};" \
	77	"erase ${monitor_base} +${filesize};" \
88461f16	78	"cp.b ${fileaddr} ${monitor_base} ${filesize};" \
1b3b7c64 JCPV	79	"protect on ${monitor_base} +${filesize}\0"
	80
	81	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	82	#define MASTER_PLL_MUL 171
	83	#define MASTER_PLL_DIV 14
1b34f00c	84	#define MASTER_PLL_OUT 3
1b3b7c64 JCPV	85
	86	/* clocks */
	87	#define CONFIG_SYS_MOR_VAL \
1b34f00c JS	88	(AT91_PMC_MOR_MOSCEN \| AT91_PMC_MOR_OSCOUNT(255))
	89	#define CONFIG_SYS_PLLAR_VAL \
	90	(AT91_PMC_PLLAR_29 \| \
	91	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) \| \
	92	AT91_PMC_PLLXR_PLLCOUNT(63) \| \
	93	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) \| \
	94	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
1b3b7c64 JCPV	95
	96	/* PCK/2 = MCK Master Clock from PLLA */
	97	#define CONFIG_SYS_MCKR1_VAL \
1b34f00c JS	98	(AT91_PMC_MCKR_CSS_SLOW \| AT91_PMC_MCKR_PRES_1 \| \
	99	AT91_PMC_MCKR_MDIV_2)
	100
1b3b7c64 JCPV	101	/* PCK/2 = MCK Master Clock from PLLA */
1b3b7c64 JCPV	102	#define CONFIG_SYS_MCKR2_VAL \
1b34f00c JS	103	(AT91_PMC_MCKR_CSS_PLLA \| AT91_PMC_MCKR_PRES_1 \| \
1b34f00c JS	104	AT91_PMC_MCKR_MDIV_2)
1b3b7c64 JCPV	105
	106	/* define PDC[31:16] as DATA[31:16] */
	107	#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
	108	/* no pull-up for D[31:16] */
	109	#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
	110	/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
1b34f00c JS	111	#define CONFIG_SYS_MATRIX_EBICSA_VAL \
	112	(AT91_MATRIX_CSA_DBPUC \| AT91_MATRIX_CSA_VDDIOMSEL_3_3V \| \
	113	AT91_MATRIX_CSA_EBI_CS1A)
1b3b7c64 JCPV	114
	115	/* SDRAM */
	116	/* SDRAMC_MR Mode register */
	117	#define CONFIG_SYS_SDRC_MR_VAL1 0
	118	/* SDRAMC_TR - Refresh Timer register */
	119	#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
	120	/* SDRAMC_CR - Configuration register*/
	121	#define CONFIG_SYS_SDRC_CR_VAL \
	122	(AT91_SDRAMC_NC_9 \| \
	123	AT91_SDRAMC_NR_13 \| \
	124	AT91_SDRAMC_NB_4 \| \
	125	AT91_SDRAMC_CAS_3 \| \
	126	AT91_SDRAMC_DBW_32 \| \
	127	(1 << 8) \| /* Write Recovery Delay */ \
	128	(7 << 12) \| /* Row Cycle Delay */ \
	129	(2 << 16) \| /* Row Precharge Delay */ \
	130	(2 << 20) \| /* Row to Column Delay */ \
	131	(5 << 24) \| /* Active to Precharge Delay */ \
	132	(1 << 28)) /* Exit Self Refresh to Active Delay */
	133
	134	/* Memory Device Register -> SDRAM */
	135	#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
	136	#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
	137	#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
	138	#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
	139	#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
	140	#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
	141	#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
	142	#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
	143	#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
	144	#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
	145	#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
	146	#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
	147	#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
	148	#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
	149	#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
	150	#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
	151	#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
	152	#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
	153
	154	/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
1b34f00c JS	155	#define CONFIG_SYS_SMC0_SETUP0_VAL \
	156	(AT91_SMC_SETUP_NWE(10) \| AT91_SMC_SETUP_NCS_WR(10) \| \
	157	AT91_SMC_SETUP_NRD(10) \| AT91_SMC_SETUP_NCS_RD(10))
	158	#define CONFIG_SYS_SMC0_PULSE0_VAL \
	159	(AT91_SMC_PULSE_NWE(11) \| AT91_SMC_PULSE_NCS_WR(11) \| \
	160	AT91_SMC_PULSE_NRD(11) \| AT91_SMC_PULSE_NCS_RD(11))
1b3b7c64	161	#define CONFIG_SYS_SMC0_CYCLE0_VAL \
1b34f00c	162	(AT91_SMC_CYCLE_NWE(22) \| AT91_SMC_CYCLE_NRD(22))
1b3b7c64	163	#define CONFIG_SYS_SMC0_MODE0_VAL \
1b34f00c JS	164	(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \| \
	165	AT91_SMC_MODE_DBW_16 \| \
	166	AT91_SMC_MODE_TDF \| AT91_SMC_MODE_TDF_CYCLE(6))
1b3b7c64 JCPV	167
	168	/* user reset enable */
	169	#define CONFIG_SYS_RSTC_RMR_VAL \
	170	(AT91_RSTC_KEY \| \
1b34f00c JS	171	AT91_RSTC_MR_URSTEN \| \
1b34f00c JS	172	AT91_RSTC_MR_ERSTL(15))
1b3b7c64 JCPV	173
	174	/* Disable Watchdog */
	175	#define CONFIG_SYS_WDTC_WDMR_VAL \
1b34f00c JS	176	(AT91_WDT_MR_WDIDLEHLT \| AT91_WDT_MR_WDDBGHLT \| \
	177	AT91_WDT_MR_WDV(0xfff) \| \
	178	AT91_WDT_MR_WDDIS \| \
	179	AT91_WDT_MR_WDD(0xfff))
	180
1b3b7c64	181	#endif
1af3c7f4	182	#include <linux/stringify.h>
8e429b3e SP	183	#endif
	184
	185	/* NAND flash */
74c076d6	186	#ifdef CONFIG_CMD_NAND
6d0f6bcf	187	#define CONFIG_SYS_MAX_NAND_DEVICE 1
cd46b0f2	188	#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
6d0f6bcf	189	#define CONFIG_SYS_NAND_DBW_8 1
74c076d6 JCPV	190	/* our ALE is AD21 */
	191	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	192	/* our CLE is AD22 */
	193	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
cd46b0f2 XH	194	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
cd46b0f2 XH	195	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
74c076d6	196	#endif
8e429b3e SP	197
8e429b3e SP	198	/* Ethernet */
8e429b3e	199	#define CONFIG_RESET_PHY_R 1
4535a24c	200	#define CONFIG_AT91_WANTS_COMMON_PHY
8e429b3e SP	201
8e429b3e SP	202	/* USB */
2b7178af	203	#define CONFIG_USB_ATMEL
dcd2f1a0	204	#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
8e429b3e	205	#define CONFIG_USB_OHCI_NEW 1
6d0f6bcf JCPV	206	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	207	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
	208	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
	209	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
8e429b3e	210
6d0f6bcf	211	#ifdef CONFIG_SYS_USE_DATAFLASH
8e429b3e SP	212
8e429b3e SP	213	/* bootstrap + u-boot + env + linux in dataflash on CS0 */
eab36f6d WY	214	#define CONFIG_BOOTCOMMAND "sf probe 0; " \
	215	"sf read 0x22000000 0x84000 0x294000; " \
	216	"bootm 0x22000000"
8e429b3e	217
1b3b7c64	218	#elif CONFIG_SYS_USE_NANDFLASH
8e429b3e SP	219
8e429b3e SP	220	/* bootstrap + u-boot + env + linux in nandflash */
0c58cfa9	221	#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
8e429b3e SP	222	#endif
8e429b3e SP	223
8e429b3e SP	224	/*
	225	* Size of malloc() pool
	226	*/
cd46b0f2	227	#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
8e429b3e	228
8e429b3e	229	#endif