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22ee6473 SG |
1 | /* |
2 | * (C) Copyright 2007-2008 | |
c9e798d3 | 3 | * Stelian Pop <stelian@popies.net> |
22ee6473 SG |
4 | * Lead Tech Design <www.leadtechdesign.com> |
5 | * | |
6 | * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES). | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
22ee6473 SG |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
5cfeec51 TP |
14 | #include <asm/hardware.h> |
15 | ||
77461a65 BS |
16 | #define CONFIG_SYS_TEXT_BASE 0x73f00000 |
17 | ||
5cfeec51 | 18 | #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ |
425de62d | 19 | |
22ee6473 | 20 | /* ARM asynchronous clock */ |
5cfeec51 TP |
21 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
22 | #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ | |
5cfeec51 TP |
23 | |
24 | #define CONFIG_AT91SAM9M10G45EK | |
22ee6473 | 25 | |
5cfeec51 TP |
26 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
27 | #define CONFIG_SETUP_MEMORY_TAGS | |
28 | #define CONFIG_INITRD_TAG | |
22ee6473 | 29 | #define CONFIG_SKIP_LOWLEVEL_INIT |
5cfeec51 TP |
30 | |
31 | /* general purpose I/O */ | |
32 | #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ | |
33 | #define CONFIG_AT91_GPIO | |
34 | #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ | |
35 | ||
36 | /* serial console */ | |
37 | #define CONFIG_ATMEL_USART | |
38 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU | |
39 | #define CONFIG_USART_ID ATMEL_ID_SYS | |
40 | ||
22ee6473 | 41 | /* LCD */ |
22ee6473 | 42 | #define LCD_BPP LCD_COLOR8 |
5cfeec51 | 43 | #define CONFIG_LCD_LOGO |
22ee6473 | 44 | #undef LCD_TEST_PATTERN |
5cfeec51 TP |
45 | #define CONFIG_LCD_INFO |
46 | #define CONFIG_LCD_INFO_BELOW_LOGO | |
47 | #define CONFIG_SYS_WHITE_ON_BLACK | |
48 | #define CONFIG_ATMEL_LCD | |
49 | #define CONFIG_ATMEL_LCD_RGB565 | |
22ee6473 SG |
50 | /* board specific(not enough SRAM) */ |
51 | #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000 | |
52 | ||
53 | /* LED */ | |
54 | #define CONFIG_AT91_LED | |
55 | #define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ | |
56 | #define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */ | |
57 | ||
22ee6473 SG |
58 | |
59 | /* | |
60 | * BOOTP options | |
61 | */ | |
5cfeec51 TP |
62 | #define CONFIG_BOOTP_BOOTFILESIZE |
63 | #define CONFIG_BOOTP_BOOTPATH | |
64 | #define CONFIG_BOOTP_GATEWAY | |
65 | #define CONFIG_BOOTP_HOSTNAME | |
22ee6473 SG |
66 | |
67 | /* | |
68 | * Command line configuration. | |
69 | */ | |
782358fb | 70 | |
5cfeec51 | 71 | #define CONFIG_CMD_NAND |
22ee6473 SG |
72 | |
73 | /* SDRAM */ | |
74 | #define CONFIG_NR_DRAM_BANKS 1 | |
5cfeec51 TP |
75 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 |
76 | #define CONFIG_SYS_SDRAM_SIZE 0x08000000 | |
22ee6473 | 77 | |
5cfeec51 TP |
78 | #define CONFIG_SYS_INIT_SP_ADDR \ |
79 | (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) | |
80 | ||
22ee6473 SG |
81 | /* NAND flash */ |
82 | #ifdef CONFIG_CMD_NAND | |
22ee6473 SG |
83 | #define CONFIG_NAND_ATMEL |
84 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
5cfeec51 TP |
85 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
86 | #define CONFIG_SYS_NAND_DBW_8 | |
22ee6473 SG |
87 | /* our ALE is AD21 */ |
88 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
89 | /* our CLE is AD22 */ | |
90 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
91 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 | |
92 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 | |
2eb99ca8 | 93 | |
22ee6473 SG |
94 | #endif |
95 | ||
cf874c19 | 96 | /* MMC */ |
cf874c19 WJ |
97 | |
98 | #ifdef CONFIG_CMD_MMC | |
cf874c19 WJ |
99 | #define CONFIG_GENERIC_ATMEL_MCI |
100 | #endif | |
101 | ||
22ee6473 | 102 | /* Ethernet */ |
5cfeec51 TP |
103 | #define CONFIG_MACB |
104 | #define CONFIG_RMII | |
22ee6473 | 105 | #define CONFIG_NET_RETRY_COUNT 20 |
5cfeec51 | 106 | #define CONFIG_RESET_PHY_R |
4535a24c | 107 | #define CONFIG_AT91_WANTS_COMMON_PHY |
22ee6473 SG |
108 | |
109 | /* USB */ | |
e1edd065 BS |
110 | #define CONFIG_USB_EHCI |
111 | #define CONFIG_USB_EHCI_ATMEL | |
112 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 | |
22ee6473 | 113 | |
5cfeec51 | 114 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
22ee6473 | 115 | |
5cfeec51 TP |
116 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
117 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 | |
22ee6473 | 118 | |
9637a1bb | 119 | #ifdef CONFIG_SYS_USE_NANDFLASH |
5cfeec51 TP |
120 | /* bootstrap + u-boot + env in nandflash */ |
121 | #define CONFIG_ENV_IS_IN_NAND | |
0c58cfa9 BS |
122 | #define CONFIG_ENV_OFFSET 0xc0000 |
123 | #define CONFIG_ENV_OFFSET_REDUND 0x100000 | |
5cfeec51 TP |
124 | #define CONFIG_ENV_SIZE 0x20000 |
125 | ||
0c58cfa9 BS |
126 | #define CONFIG_BOOTCOMMAND \ |
127 | "nand read 0x70000000 0x200000 0x300000;" \ | |
5cfeec51 TP |
128 | "bootm 0x70000000" |
129 | #define CONFIG_BOOTARGS \ | |
130 | "console=ttyS0,115200 earlyprintk " \ | |
0c58cfa9 BS |
131 | "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ |
132 | "256k(env),256k(env_redundant),256k(spare)," \ | |
133 | "512k(dtb),6M(kernel)ro,-(rootfs) " \ | |
134 | "root=/dev/mtdblock7 rw rootfstype=jffs2" | |
9637a1bb WJ |
135 | #elif CONFIG_SYS_USE_MMC |
136 | /* bootstrap + u-boot + env + linux in mmc */ | |
137 | #define FAT_ENV_INTERFACE "mmc" | |
be354c1a WJ |
138 | /* |
139 | * We don't specify the part number, if device 0 has partition table, it means | |
140 | * the first partition; it no partition table, then take whole device as a | |
141 | * FAT file system. | |
142 | */ | |
143 | #define FAT_ENV_DEVICE_AND_PART "0" | |
9637a1bb WJ |
144 | #define FAT_ENV_FILE "uboot.env" |
145 | #define CONFIG_ENV_IS_IN_FAT | |
146 | #define CONFIG_FAT_WRITE | |
147 | #define CONFIG_ENV_SIZE 0x4000 | |
148 | ||
149 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ | |
150 | "mtdparts=atmel_nand:" \ | |
151 | "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \ | |
152 | "root=/dev/mmcblk0p2 rw rootwait" | |
153 | #define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \ | |
154 | "fatload mmc 0:1 0x72000000 zImage; " \ | |
155 | "bootz 0x72000000 - 0x71000000" | |
156 | #endif | |
5cfeec51 TP |
157 | |
158 | #define CONFIG_BAUDRATE 115200 | |
22ee6473 | 159 | |
22ee6473 SG |
160 | #define CONFIG_SYS_CBSIZE 256 |
161 | #define CONFIG_SYS_MAXARGS 16 | |
5cfeec51 TP |
162 | #define CONFIG_SYS_LONGHELP |
163 | #define CONFIG_CMDLINE_EDITING | |
22ee6473 | 164 | #define CONFIG_AUTO_COMPLETE |
22ee6473 | 165 | |
22ee6473 SG |
166 | /* |
167 | * Size of malloc() pool | |
168 | */ | |
169 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) | |
22ee6473 | 170 | |
41d41a93 BS |
171 | /* Defines for SPL */ |
172 | #define CONFIG_SPL_FRAMEWORK | |
173 | #define CONFIG_SPL_TEXT_BASE 0x300000 | |
174 | #define CONFIG_SPL_MAX_SIZE 0x010000 | |
175 | #define CONFIG_SPL_STACK 0x310000 | |
176 | ||
41d41a93 BS |
177 | #define CONFIG_SYS_MONITOR_LEN 0x80000 |
178 | ||
179 | #ifdef CONFIG_SYS_USE_MMC | |
180 | ||
181 | #define CONFIG_SPL_BSS_START_ADDR 0x70000000 | |
182 | #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 | |
183 | #define CONFIG_SYS_SPL_MALLOC_START 0x70080000 | |
184 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 | |
185 | ||
186 | #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | |
41d41a93 BS |
187 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
188 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" | |
41d41a93 BS |
189 | |
190 | #elif CONFIG_SYS_USE_NANDFLASH | |
41d41a93 BS |
191 | #define CONFIG_SPL_NAND_DRIVERS |
192 | #define CONFIG_SPL_NAND_BASE | |
193 | #define CONFIG_SPL_NAND_ECC | |
194 | #define CONFIG_SPL_NAND_SOFTECC | |
195 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 | |
196 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 | |
197 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
198 | ||
199 | #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 | |
200 | #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 | |
201 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
202 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
203 | #define CONFIG_SYS_NAND_ECCSIZE 256 | |
204 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
205 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
206 | #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ | |
207 | 48, 49, 50, 51, 52, 53, 54, 55, \ | |
208 | 56, 57, 58, 59, 60, 61, 62, 63, } | |
209 | #endif | |
210 | ||
211 | #define CONFIG_SPL_ATMEL_SIZE | |
212 | #define CONFIG_SYS_MASTER_CLOCK 132096000 | |
213 | #define CONFIG_SYS_AT91_PLLA 0x20c73f03 | |
214 | #define CONFIG_SYS_MCKR 0x1301 | |
215 | #define CONFIG_SYS_MCKR_CSS 0x1302 | |
216 | ||
22ee6473 | 217 | #endif |