[people/ms/u-boot.git] / include / configs / atc.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_ATC		1	/* ...on a ATC board	*/
#define CONFIG_CPM2		1	/* Has a CPM2 */

#define	CONFIG_SYS_TEXT_BASE	0xFF000000

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#define  CONFIG_CONS_ON_SMC		/* define if console on SMC */
#undef CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef  CONFIG_CONS_NONE		/* define if console on something else*/
#define CONFIG_CONS_INDEX	2	/* which serial channel for console */

#define CONFIG_BAUDRATE		115200

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
#define CONFIG_ETHER_ON_FCC

#define CONFIG_ETHER_ON_FCC2

/*
 * - Rx-CLK is CLK13
 * - Tx-CLK is CLK14
 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 * - Enable Full Duplex in FSMR
 */
# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
# define CONFIG_SYS_CPMFCR_RAMTYPE	0
# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)

#define CONFIG_ETHER_ON_FCC3

/*
 * - Rx-CLK is CLK15
 * - Tx-CLK is CLK16
 * - RAM for BD/Buffers is on the local Bus (see 28-13)
 * - Enable Half Duplex in FSMR
 */
# define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
# define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)

/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	64000000	/* in Hz */

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#undef	CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in Hz */

#define CONFIG_PREBOOT							\
	"echo;"								\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
	"echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND						\
	"bootp;"							\
	"setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=${serverip}:${rootpath} "				\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
	"bootm"

/*-----------------------------------------------------------------------
 * Miscellaneous configuration options
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_DATE
#define CONFIG_CMD_IDE


#define CONFIG_DOS_PARTITION

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/

#define CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/

#define	CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/

#define CONFIG_SYS_ALLOC_DPRAM

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SPI

#define CONFIG_RTC_DS12887

#define RTC_BASE_ADDR		0xF5000000
#define RTC_PORT_ADDR		RTC_BASE_ADDR + 0x800
#define RTC_PORT_DATA		RTC_BASE_ADDR + 0x808

#define CONFIG_MISC_INIT_R

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * Flash configuration
 */

#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_FLASH_SIZE		0x00800000

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#define CONFIG_FLASH_16BIT

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 */
#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
				 HRCW_BPS10 |\
				 HRCW_APPC10)

/* no slaves so just fill with zeros */
#define CONFIG_SYS_HRCW_SLAVE1		0
#define CONFIG_SYS_HRCW_SLAVE2		0
#define CONFIG_SYS_HRCW_SLAVE3		0
#define CONFIG_SYS_HRCW_SLAVE4		0
#define CONFIG_SYS_HRCW_SLAVE5		0
#define CONFIG_SYS_HRCW_SLAVE6		0
#define CONFIG_SYS_HRCW_SLAVE7		0

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00  /* Size of used area in DPRAM    */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 *
 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT
#endif

#define	CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define	CONFIG_PCI_PNP
#define	CONFIG_SYS_PCI_MSTR_IO_BUS	0x00000000	/* PCI base   */

#if 1
/* environment is in Flash */
#define CONFIG_ENV_IS_IN_FLASH	1
# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x30000)
# define CONFIG_ENV_SIZE		0x10000
# define CONFIG_ENV_SECT_SIZE	0x10000
#else
#define CONFIG_ENV_IS_IN_EEPROM	1
#define CONFIG_ENV_OFFSET		0
#define CONFIG_ENV_SIZE		2048
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 16-byte page size	*/
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers                    2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
			 HID0_DCI|HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID2        0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register                                     5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CONFIG_SYS_RMR         RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration                                       4-25
 *-----------------------------------------------------------------------
 */
#define BCR_APD01	0x10000000
#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration                             4-31
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_APPC10|\
			 SIUMCR_CS10PC00|SIUMCR_BCTLC10)

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control                             4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control                     4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control                 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control                                   9-8
 *-----------------------------------------------------------------------
 * Ensure DFBRG is Divide by 16
 */
#define CONFIG_SYS_SCCR        SCCR_DFBRG01

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration                         13-7
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RCCR        0

#define CONFIG_SYS_MIN_AM_MASK	0xC0000000
/*-----------------------------------------------------------------------
 * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_MPTPR       0x1F00

/*-----------------------------------------------------------------------
 * PSRT - Refresh Timer Register                                10-16
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_PSRT        0x0f

/*-----------------------------------------------------------------------
 * PSRT - SDRAM Mode Register                                   10-10
 *-----------------------------------------------------------------------
 */

	/* SDRAM initialization values for 8-column chips
	 */
#define CONFIG_SYS_OR2_8COL	(CONFIG_SYS_MIN_AM_MASK		|\
			 ORxS_BPD_4			|\
			 ORxS_ROWST_PBI1_A7		|\
			 ORxS_NUMR_12)

#define CONFIG_SYS_PSDMR_8COL	(PSDMR_PBI			|\
			 PSDMR_SDAM_A15_IS_A5		|\
			 PSDMR_BSMA_A15_A17		|\
			 PSDMR_SDA10_PBI1_A7		|\
			 PSDMR_RFRC_7_CLK		|\
			 PSDMR_PRETOACT_3W		|\
			 PSDMR_ACTTORW_2W		|\
			 PSDMR_LDOTOPRE_1C		|\
			 PSDMR_WRC_1C			|\
			 PSDMR_CL_2)

	/* SDRAM initialization values for 9-column chips
	 */
#define CONFIG_SYS_OR2_9COL	(CONFIG_SYS_MIN_AM_MASK		|\
			 ORxS_BPD_4			|\
			 ORxS_ROWST_PBI1_A6		|\
			 ORxS_NUMR_12)

#define CONFIG_SYS_PSDMR_9COL	(PSDMR_PBI			|\
			 PSDMR_SDAM_A16_IS_A5		|\
			 PSDMR_BSMA_A15_A17		|\
			 PSDMR_SDA10_PBI1_A6		|\
			 PSDMR_RFRC_7_CLK		|\
			 PSDMR_PRETOACT_3W		|\
			 PSDMR_ACTTORW_2W		|\
			 PSDMR_LDOTOPRE_1C		|\
			 PSDMR_WRC_1C			|\
			 PSDMR_CL_2)

/*
 * Init Memory Controller:
 *
 * Bank Bus     Machine PortSz  Device
 * ---- ---     ------- ------  ------
 *  0   60x     GPCM    8  bit  Boot ROM
 *  1   60x     GPCM    64 bit  FLASH
 *  2   60x     SDRAM   64 bit  SDRAM
 *
 */

#define CONFIG_SYS_MRS_OFFS	0x00000000

/* Bank 0 - FLASH
 */
#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
			 BRx_PS_16                      |\
			 BRx_MS_GPCM_P                  |\
			 BRx_V)

#define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
			 ORxG_CSNT                      |\
			 ORxG_ACS_DIV1                  |\
			 ORxG_SCY_3_CLK                 |\
			 ORxU_EHTR_8IDLE)


/* Bank 2 - 60x bus SDRAM
 */
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
			 BRx_PS_64                      |\
			 BRx_MS_SDRAM_P                 |\
			 BRx_V)

#define CONFIG_SYS_OR2_PRELIM	 CONFIG_SYS_OR2_8COL

#define CONFIG_SYS_PSDMR	 CONFIG_SYS_PSDMR_8COL
#endif /* CONFIG_SYS_RAMBOOT */

#define CONFIG_SYS_BR4_PRELIM  ((RTC_BASE_ADDR & BRx_BA_MSK)   |\
			 BRx_PS_8                       |\
			 BRx_MS_UPMA                    |\
			 BRx_V)

#define CONFIG_SYS_OR4_PRELIM  (ORxU_AM_MSK | ORxU_BI)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_I82365

#define CONFIG_SYS_PCMCIA_MEM_ADDR	0x81000000
#define CONFIG_SYS_PCMCIA_MEM_SIZE	0x1000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	0xa0000000

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	0x100

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	0x100

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x108

#endif	/* __CONFIG_H */
Commit	Line	Data
7aa78614 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
7aa78614 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
7aa78614	20	#define CONFIG_ATC 1 /* ...on a ATC board */
9c4c5ae3	21	#define CONFIG_CPM2 1 /* Has a CPM2 */
7aa78614	22
2ae18241 WD	23	#define CONFIG_SYS_TEXT_BASE 0xFF000000
2ae18241 WD	24
7aa78614 WD	25	/*
	26	* select serial console configuration
	27	*
	28	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	29	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	30	* for SCC).
	31	*
	32	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	33	* defined elsewhere (for example, on the cogent platform, there are serial
	34	* ports on the motherboard which are used for the serial console - see
	35	* cogent/cma101/serial.[ch]).
	36	*/
	37	#define CONFIG_CONS_ON_SMC /* define if console on SMC */
	38	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
	39	#undef CONFIG_CONS_NONE /* define if console on something else*/
	40	#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
	41
	42	#define CONFIG_BAUDRATE 115200
	43
	44	/*
	45	* select ethernet configuration
	46	*
	47	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	48	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	49	* for FCC)
	50	*
	51	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7	52	* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
7aa78614 WD	53	*/
	54	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
	55	#undef CONFIG_ETHER_NONE /* define if ether on something else */
	56	#define CONFIG_ETHER_ON_FCC
	57
7aa78614 WD	58	#define CONFIG_ETHER_ON_FCC2
	59
	60	/*
	61	* - Rx-CLK is CLK13
	62	* - Tx-CLK is CLK14
	63	* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
	64	* - Enable Full Duplex in FSMR
	65	*/
6d0f6bcf JCPV	66	# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2\|CMXFCR_RF2CS_MSK\|CMXFCR_TF2CS_MSK)
	67	# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13\|CMXFCR_TF2CS_CLK14)
	68	# define CONFIG_SYS_CPMFCR_RAMTYPE 0
	69	# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE\|FCC_PSMR_LPB)
7aa78614 WD	70
	71	#define CONFIG_ETHER_ON_FCC3
	72
	73	/*
	74	* - Rx-CLK is CLK15
	75	* - Tx-CLK is CLK16
	76	* - RAM for BD/Buffers is on the local Bus (see 28-13)
	77	* - Enable Half Duplex in FSMR
	78	*/
6d0f6bcf JCPV	79	# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3\|CMXFCR_RF3CS_MSK\|CMXFCR_TF3CS_MSK)
6d0f6bcf JCPV	80	# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15\|CMXFCR_TF3CS_CLK16)
7aa78614 WD	81
	82	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
	83	#define CONFIG_8260_CLKIN 64000000 /* in Hz */
	84
	85	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	86
	87	#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
	88
	89	#define CONFIG_PREBOOT \
	90	"echo;" \
32bf3d14	91	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
7aa78614 WD	92	"echo"
	93
	94	#undef CONFIG_BOOTARGS
	95	#define CONFIG_BOOTCOMMAND \
	96	"bootp;" \
	97	"setenv bootargs root=/dev/nfs rw " \
53677ef1	98	"nfsroot=${serverip}:${rootpath} " \
fe126d8b	99	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
7aa78614 WD	100	"bootm"
	101
	102	/*-----------------------------------------------------------------------
	103	* Miscellaneous configuration options
	104	*/
	105
	106	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	107	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
7aa78614	108
2fd90ce5 JL	109
	110	/*
	111	* BOOTP options
	112	*/
	113	#define CONFIG_BOOTP_SUBNETMASK
	114	#define CONFIG_BOOTP_GATEWAY
	115	#define CONFIG_BOOTP_HOSTNAME
	116	#define CONFIG_BOOTP_BOOTPATH
	117	#define CONFIG_BOOTP_BOOTFILESIZE
7aa78614	118
15ef8a5d	119
0b361c91 JL	120	/*
	121	* Command line configuration.
	122	*/
	123	#include <config_cmd_default.h>
15ef8a5d	124
0b361c91 JL	125	#define CONFIG_CMD_EEPROM
	126	#define CONFIG_CMD_PCI
	127	#define CONFIG_CMD_PCMCIA
	128	#define CONFIG_CMD_DATE
	129	#define CONFIG_CMD_IDE
7aa78614	130
0b361c91 JL	131
0b361c91 JL	132	#define CONFIG_DOS_PARTITION
7aa78614 WD	133
	134	/*
	135	* Miscellaneous configurable options
	136	*/
6d0f6bcf	137	#define CONFIG_SYS_LONGHELP /* undef to save memory */
0b361c91	138	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	139	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
7aa78614	140	#else
6d0f6bcf	141	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
7aa78614	142	#endif
6d0f6bcf JCPV	143	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	144	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	145	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
7aa78614	146
6d0f6bcf JCPV	147	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	148	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
7aa78614	149
6d0f6bcf	150	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
7aa78614	151
6d0f6bcf	152	#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
66fd3d1c	153
6d0f6bcf	154	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
7aa78614	155
6d0f6bcf	156	#define CONFIG_SYS_ALLOC_DPRAM
7aa78614 WD	157
	158	#undef CONFIG_WATCHDOG /* watchdog disabled */
	159
	160	#define CONFIG_SPI
	161
15ef8a5d WD	162	#define CONFIG_RTC_DS12887
15ef8a5d WD	163
53677ef1 WD	164	#define RTC_BASE_ADDR 0xF5000000
	165	#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
	166	#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
15ef8a5d WD	167
	168	#define CONFIG_MISC_INIT_R
	169
7aa78614 WD	170	/*
	171	* For booting Linux, the board info and command line data
	172	* have to be in the first 8 MB of memory, since this is
	173	* the maximum mapped by the Linux kernel during initialization.
	174	*/
6d0f6bcf	175	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
7aa78614 WD	176
	177	/*-----------------------------------------------------------------------
	178	* Flash configuration
	179	*/
	180
6d0f6bcf JCPV	181	#define CONFIG_SYS_FLASH_BASE 0xFF000000
6d0f6bcf JCPV	182	#define CONFIG_SYS_FLASH_SIZE 0x00800000
7aa78614 WD	183
	184	/*-----------------------------------------------------------------------
	185	* FLASH organization
	186	*/
6d0f6bcf JCPV	187	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
6d0f6bcf JCPV	188	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
7aa78614	189
6d0f6bcf JCPV	190	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	191	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
7aa78614 WD	192
	193	#define CONFIG_FLASH_16BIT
	194
	195	/*-----------------------------------------------------------------------
	196	* Hard Reset Configuration Words
	197	*
6d0f6bcf	198	* if you change bits in the HRCW, you must also change the CONFIG_SYS_*
7aa78614	199	* defines for the various registers affected by the HRCW e.g. changing
6d0f6bcf	200	* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
7aa78614	201	*/
6d0f6bcf	202	#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP \| HRCW_ISB100 \| HRCW_BMS \| \
9a0e21a3	203	HRCW_BPS10 \|\
7aa78614 WD	204	HRCW_APPC10)
	205
	206	/* no slaves so just fill with zeros */
6d0f6bcf JCPV	207	#define CONFIG_SYS_HRCW_SLAVE1 0
	208	#define CONFIG_SYS_HRCW_SLAVE2 0
	209	#define CONFIG_SYS_HRCW_SLAVE3 0
	210	#define CONFIG_SYS_HRCW_SLAVE4 0
	211	#define CONFIG_SYS_HRCW_SLAVE5 0
	212	#define CONFIG_SYS_HRCW_SLAVE6 0
	213	#define CONFIG_SYS_HRCW_SLAVE7 0
7aa78614 WD	214
	215	/*-----------------------------------------------------------------------
	216	* Internal Memory Mapped Register
	217	*/
6d0f6bcf	218	#define CONFIG_SYS_IMMR 0xF0000000
7aa78614 WD	219
	220	/*-----------------------------------------------------------------------
	221	* Definitions for initial stack pointer and data area (in DPRAM)
	222	*/
6d0f6bcf	223	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	224	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	225	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	226	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
7aa78614 WD	227
	228	/*-----------------------------------------------------------------------
	229	* Start addresses for the final memory configuration
	230	* (Set up by the startup code)
6d0f6bcf	231	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
7aa78614	232	*
6d0f6bcf	233	* 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
7aa78614	234	*/
6d0f6bcf JCPV	235	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	236	#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
14d0a02a	237	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	238	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
6d0f6bcf JCPV	239	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
7aa78614	240
6d0f6bcf JCPV	241	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	242	# define CONFIG_SYS_RAMBOOT
7aa78614 WD	243	#endif
7aa78614 WD	244
66fd3d1c	245	#define CONFIG_PCI
842033e6	246	#define CONFIG_PCI_INDIRECT_BRIDGE
66fd3d1c	247	#define CONFIG_PCI_PNP
6d0f6bcf	248	#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
66fd3d1c	249
7aa78614 WD	250	#if 1
7aa78614 WD	251	/* environment is in Flash */
5a1aceb0	252	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	253	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x30000)
0e8d1586 JCPV	254	# define CONFIG_ENV_SIZE 0x10000
0e8d1586 JCPV	255	# define CONFIG_ENV_SECT_SIZE 0x10000
7aa78614	256	#else
bb1f8b4f	257	#define CONFIG_ENV_IS_IN_EEPROM 1
0e8d1586 JCPV	258	#define CONFIG_ENV_OFFSET 0
0e8d1586 JCPV	259	#define CONFIG_ENV_SIZE 2048
6d0f6bcf	260	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
7aa78614	261	#endif
7aa78614 WD	262
	263	/*-----------------------------------------------------------------------
	264	* Cache Configuration
	265	*/
6d0f6bcf	266	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
0b361c91	267	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	268	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
7aa78614 WD	269	#endif
	270
	271	/*-----------------------------------------------------------------------
	272	* HIDx - Hardware Implementation-dependent Registers 2-11
	273	*-----------------------------------------------------------------------
	274	* HID0 also contains cache control - initially enable both caches and
	275	* invalidate contents, then the final state leaves only the instruction
	276	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
	277	* but Soft reset does not.
	278	*
	279	* HID1 has only read-only information - nothing to set.
	280	*/
6d0f6bcf	281	#define CONFIG_SYS_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|\
8bde7f77	282	HID0_DCI\|HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	283	#define CONFIG_SYS_HID0_FINAL (HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	284	#define CONFIG_SYS_HID2 0
7aa78614 WD	285
	286	/*-----------------------------------------------------------------------
	287	* RMR - Reset Mode Register 5-5
	288	*-----------------------------------------------------------------------
	289	* turn on Checkstop Reset Enable
	290	*/
6d0f6bcf	291	#define CONFIG_SYS_RMR RMR_CSRE
7aa78614 WD	292
	293	/*-----------------------------------------------------------------------
	294	* BCR - Bus Configuration 4-25
	295	*-----------------------------------------------------------------------
	296	*/
	297	#define BCR_APD01 0x10000000
6d0f6bcf	298	#define CONFIG_SYS_BCR (BCR_APD01\|BCR_ETM\|BCR_LETM) /* 8260 mode */
7aa78614 WD	299
	300	/*-----------------------------------------------------------------------
	301	* SIUMCR - SIU Module Configuration 4-31
	302	*-----------------------------------------------------------------------
	303	*/
6d0f6bcf	304	#define CONFIG_SYS_SIUMCR (SIUMCR_BBD\|SIUMCR_APPC10\|\
7aa78614 WD	305	SIUMCR_CS10PC00\|SIUMCR_BCTLC10)
	306
	307	/*-----------------------------------------------------------------------
	308	* SYPCR - System Protection Control 4-35
	309	* SYPCR can only be written once after reset!
	310	*-----------------------------------------------------------------------
	311	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	312	*/
	313	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	314	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
8bde7f77	315	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
7aa78614	316	#else
6d0f6bcf	317	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
8bde7f77	318	SYPCR_SWRI\|SYPCR_SWP)
7aa78614 WD	319	#endif /* CONFIG_WATCHDOG */
	320
	321	/*-----------------------------------------------------------------------
	322	* TMCNTSC - Time Counter Status and Control 4-40
	323	*-----------------------------------------------------------------------
	324	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	325	* and enable Time Counter
	326	*/
6d0f6bcf	327	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
7aa78614 WD	328
	329	/*-----------------------------------------------------------------------
	330	* PISCR - Periodic Interrupt Status and Control 4-42
	331	*-----------------------------------------------------------------------
	332	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	333	* Periodic timer
	334	*/
6d0f6bcf	335	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
7aa78614 WD	336
	337	/*-----------------------------------------------------------------------
	338	* SCCR - System Clock Control 9-8
	339	*-----------------------------------------------------------------------
	340	* Ensure DFBRG is Divide by 16
	341	*/
6d0f6bcf	342	#define CONFIG_SYS_SCCR SCCR_DFBRG01
7aa78614 WD	343
	344	/*-----------------------------------------------------------------------
	345	* RCCR - RISC Controller Configuration 13-7
	346	*-----------------------------------------------------------------------
	347	*/
6d0f6bcf	348	#define CONFIG_SYS_RCCR 0
7aa78614	349
6d0f6bcf	350	#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
7aa78614 WD	351	/*-----------------------------------------------------------------------
	352	* MPTPR - Memory Refresh Timer Prescaler Register 10-18
	353	*-----------------------------------------------------------------------
	354	*/
6d0f6bcf	355	#define CONFIG_SYS_MPTPR 0x1F00
7aa78614 WD	356
	357	/*-----------------------------------------------------------------------
	358	* PSRT - Refresh Timer Register 10-16
	359	*-----------------------------------------------------------------------
	360	*/
6d0f6bcf	361	#define CONFIG_SYS_PSRT 0x0f
7aa78614 WD	362
	363	/*-----------------------------------------------------------------------
	364	* PSRT - SDRAM Mode Register 10-10
	365	*-----------------------------------------------------------------------
	366	*/
	367
	368	/* SDRAM initialization values for 8-column chips
	369	*/
6d0f6bcf	370	#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK \|\
7aa78614	371	ORxS_BPD_4 \|\
f7de16ae WD	372	ORxS_ROWST_PBI1_A7 \|\
f7de16ae WD	373	ORxS_NUMR_12)
7aa78614	374
6d0f6bcf	375	#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI \|\
f7de16ae WD	376	PSDMR_SDAM_A15_IS_A5 \|\
	377	PSDMR_BSMA_A15_A17 \|\
	378	PSDMR_SDA10_PBI1_A7 \|\
7aa78614	379	PSDMR_RFRC_7_CLK \|\
f7de16ae WD	380	PSDMR_PRETOACT_3W \|\
f7de16ae WD	381	PSDMR_ACTTORW_2W \|\
7aa78614 WD	382	PSDMR_LDOTOPRE_1C \|\
	383	PSDMR_WRC_1C \|\
	384	PSDMR_CL_2)
	385
	386	/* SDRAM initialization values for 9-column chips
	387	*/
6d0f6bcf	388	#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK \|\
7aa78614	389	ORxS_BPD_4 \|\
f7de16ae WD	390	ORxS_ROWST_PBI1_A6 \|\
f7de16ae WD	391	ORxS_NUMR_12)
7aa78614	392
6d0f6bcf	393	#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI \|\
f7de16ae WD	394	PSDMR_SDAM_A16_IS_A5 \|\
	395	PSDMR_BSMA_A15_A17 \|\
	396	PSDMR_SDA10_PBI1_A6 \|\
7aa78614	397	PSDMR_RFRC_7_CLK \|\
f7de16ae WD	398	PSDMR_PRETOACT_3W \|\
f7de16ae WD	399	PSDMR_ACTTORW_2W \|\
7aa78614 WD	400	PSDMR_LDOTOPRE_1C \|\
	401	PSDMR_WRC_1C \|\
	402	PSDMR_CL_2)
	403
	404	/*
	405	* Init Memory Controller:
	406	*
	407	* Bank Bus Machine PortSz Device
	408	* ---- --- ------- ------ ------
	409	* 0 60x GPCM 8 bit Boot ROM
	410	* 1 60x GPCM 64 bit FLASH
	411	* 2 60x SDRAM 64 bit SDRAM
	412	*
	413	*/
	414
6d0f6bcf	415	#define CONFIG_SYS_MRS_OFFS 0x00000000
7aa78614 WD	416
	417	/* Bank 0 - FLASH
	418	*/
6d0f6bcf	419	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	420	BRx_PS_16 \|\
	421	BRx_MS_GPCM_P \|\
	422	BRx_V)
7aa78614	423
6d0f6bcf	424	#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) \|\
8bde7f77 WD	425	ORxG_CSNT \|\
	426	ORxG_ACS_DIV1 \|\
	427	ORxG_SCY_3_CLK \|\
	428	ORxU_EHTR_8IDLE)
7aa78614 WD	429
	430
	431	/* Bank 2 - 60x bus SDRAM
	432	*/
6d0f6bcf JCPV	433	#ifndef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	434	#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	435	BRx_PS_64 \|\
	436	BRx_MS_SDRAM_P \|\
	437	BRx_V)
7aa78614	438
6d0f6bcf	439	#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
7aa78614	440
6d0f6bcf JCPV	441	#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL
6d0f6bcf JCPV	442	#endif /* CONFIG_SYS_RAMBOOT */
7aa78614	443
6d0f6bcf	444	#define CONFIG_SYS_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) \|\
8bde7f77 WD	445	BRx_PS_8 \|\
	446	BRx_MS_UPMA \|\
	447	BRx_V)
15ef8a5d	448
6d0f6bcf	449	#define CONFIG_SYS_OR4_PRELIM (ORxU_AM_MSK \| ORxU_BI)
8bde7f77	450
66fd3d1c WD	451	/*-----------------------------------------------------------------------
	452	* PCMCIA stuff
	453	*-----------------------------------------------------------------------
	454	*
	455	*/
	456	#define CONFIG_I82365
	457
6d0f6bcf JCPV	458	#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x81000000
6d0f6bcf JCPV	459	#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000
66fd3d1c WD	460
	461	/*-----------------------------------------------------------------------
	462	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	463	*-----------------------------------------------------------------------
	464	*/
	465
8d1165e1	466	#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
66fd3d1c WD	467	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	468
	469	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	470	#undef CONFIG_IDE_LED /* LED for ide not supported */
	471	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	472
6d0f6bcf JCPV	473	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	474	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
66fd3d1c	475
6d0f6bcf	476	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
66fd3d1c	477
6d0f6bcf	478	#define CONFIG_SYS_ATA_BASE_ADDR 0xa0000000
66fd3d1c WD	479
66fd3d1c WD	480	/* Offset for data I/O */
6d0f6bcf	481	#define CONFIG_SYS_ATA_DATA_OFFSET 0x100
66fd3d1c WD	482
66fd3d1c WD	483	/* Offset for normal register accesses */
6d0f6bcf	484	#define CONFIG_SYS_ATA_REG_OFFSET 0x100
66fd3d1c WD	485
66fd3d1c WD	486	/* Offset for alternate registers */
6d0f6bcf	487	#define CONFIG_SYS_ATA_ALT_OFFSET 0x108
66fd3d1c	488
7aa78614	489	#endif /* __CONFIG_H */