[people/ms/u-boot.git] / include / configs / atc.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
#define CONFIG_ATC		1	/* ...on a ATC board	*/
#define CONFIG_CPM2		1	/* Has a CPM2 */

#define	CONFIG_SYS_TEXT_BASE	0xFF000000

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#define  CONFIG_CONS_ON_SMC		/* define if console on SMC */
#undef CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef  CONFIG_CONS_NONE		/* define if console on something else*/
#define CONFIG_CONS_INDEX	2	/* which serial channel for console */

#define CONFIG_BAUDRATE		115200

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
#define CONFIG_ETHER_ON_FCC

#define CONFIG_ETHER_ON_FCC2

/*
 * - Rx-CLK is CLK13
 * - Tx-CLK is CLK14
 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 * - Enable Full Duplex in FSMR
 */
# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
# define CONFIG_SYS_CPMFCR_RAMTYPE	0
# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)

#define CONFIG_ETHER_ON_FCC3

/*
 * - Rx-CLK is CLK15
 * - Tx-CLK is CLK16
 * - RAM for BD/Buffers is on the local Bus (see 28-13)
 * - Enable Half Duplex in FSMR
 */
# define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
# define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)

/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	64000000	/* in Hz */

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#undef	CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in Hz */

#define CONFIG_PREBOOT							\
	"echo;"								\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
	"echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND						\
	"bootp;"							\
	"setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=${serverip}:${rootpath} "				\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
	"bootm"

/*-----------------------------------------------------------------------
 * Miscellaneous configuration options
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_DATE
#define CONFIG_CMD_IDE


#define CONFIG_DOS_PARTITION

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/

#define CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define	CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/

#define CONFIG_SYS_ALLOC_DPRAM

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SPI

#define CONFIG_RTC_DS12887

#define RTC_BASE_ADDR		0xF5000000
#define RTC_PORT_ADDR		RTC_BASE_ADDR + 0x800
#define RTC_PORT_DATA		RTC_BASE_ADDR + 0x808

#define CONFIG_MISC_INIT_R

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * Flash configuration
 */

#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_FLASH_SIZE		0x00800000

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#define CONFIG_FLASH_16BIT

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 */
#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
				 HRCW_BPS10 |\
				 HRCW_APPC10)

/* no slaves so just fill with zeros */
#define CONFIG_SYS_HRCW_SLAVE1		0
#define CONFIG_SYS_HRCW_SLAVE2		0
#define CONFIG_SYS_HRCW_SLAVE3		0
#define CONFIG_SYS_HRCW_SLAVE4		0
#define CONFIG_SYS_HRCW_SLAVE5		0
#define CONFIG_SYS_HRCW_SLAVE6		0
#define CONFIG_SYS_HRCW_SLAVE7		0

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00  /* Size of used area in DPRAM    */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 *
 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT
#endif

#define	CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define	CONFIG_PCI_PNP
#define	CONFIG_SYS_PCI_MSTR_IO_BUS	0x00000000	/* PCI base   */

#if 1
/* environment is in Flash */
#define CONFIG_ENV_IS_IN_FLASH	1
# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x30000)
# define CONFIG_ENV_SIZE		0x10000
# define CONFIG_ENV_SECT_SIZE	0x10000
#else
#define CONFIG_ENV_IS_IN_EEPROM	1
#define CONFIG_ENV_OFFSET		0
#define CONFIG_ENV_SIZE		2048
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 16-byte page size	*/
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers                    2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
			 HID0_DCI|HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID2        0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register                                     5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CONFIG_SYS_RMR         RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration                                       4-25
 *-----------------------------------------------------------------------
 */
#define BCR_APD01	0x10000000
#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration                             4-31
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_APPC10|\
			 SIUMCR_CS10PC00|SIUMCR_BCTLC10)

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control                             4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control                     4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control                 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control                                   9-8
 *-----------------------------------------------------------------------
 * Ensure DFBRG is Divide by 16
 */
#define CONFIG_SYS_SCCR        SCCR_DFBRG01

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration                         13-7
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RCCR        0

#define CONFIG_SYS_MIN_AM_MASK	0xC0000000
/*-----------------------------------------------------------------------
 * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_MPTPR       0x1F00

/*-----------------------------------------------------------------------
 * PSRT - Refresh Timer Register                                10-16
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_PSRT        0x0f

/*-----------------------------------------------------------------------
 * PSRT - SDRAM Mode Register                                   10-10
 *-----------------------------------------------------------------------
 */

	/* SDRAM initialization values for 8-column chips
	 */
#define CONFIG_SYS_OR2_8COL	(CONFIG_SYS_MIN_AM_MASK		|\
			 ORxS_BPD_4			|\
			 ORxS_ROWST_PBI1_A7		|\
			 ORxS_NUMR_12)

#define CONFIG_SYS_PSDMR_8COL	(PSDMR_PBI			|\
			 PSDMR_SDAM_A15_IS_A5		|\
			 PSDMR_BSMA_A15_A17		|\
			 PSDMR_SDA10_PBI1_A7		|\
			 PSDMR_RFRC_7_CLK		|\
			 PSDMR_PRETOACT_3W		|\
			 PSDMR_ACTTORW_2W		|\
			 PSDMR_LDOTOPRE_1C		|\
			 PSDMR_WRC_1C			|\
			 PSDMR_CL_2)

	/* SDRAM initialization values for 9-column chips
	 */
#define CONFIG_SYS_OR2_9COL	(CONFIG_SYS_MIN_AM_MASK		|\
			 ORxS_BPD_4			|\
			 ORxS_ROWST_PBI1_A6		|\
			 ORxS_NUMR_12)

#define CONFIG_SYS_PSDMR_9COL	(PSDMR_PBI			|\
			 PSDMR_SDAM_A16_IS_A5		|\
			 PSDMR_BSMA_A15_A17		|\
			 PSDMR_SDA10_PBI1_A6		|\
			 PSDMR_RFRC_7_CLK		|\
			 PSDMR_PRETOACT_3W		|\
			 PSDMR_ACTTORW_2W		|\
			 PSDMR_LDOTOPRE_1C		|\
			 PSDMR_WRC_1C			|\
			 PSDMR_CL_2)

/*
 * Init Memory Controller:
 *
 * Bank Bus     Machine PortSz  Device
 * ---- ---     ------- ------  ------
 *  0   60x     GPCM    8  bit  Boot ROM
 *  1   60x     GPCM    64 bit  FLASH
 *  2   60x     SDRAM   64 bit  SDRAM
 *
 */

#define CONFIG_SYS_MRS_OFFS	0x00000000

/* Bank 0 - FLASH
 */
#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
			 BRx_PS_16                      |\
			 BRx_MS_GPCM_P                  |\
			 BRx_V)

#define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
			 ORxG_CSNT                      |\
			 ORxG_ACS_DIV1                  |\
			 ORxG_SCY_3_CLK                 |\
			 ORxU_EHTR_8IDLE)


/* Bank 2 - 60x bus SDRAM
 */
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
			 BRx_PS_64                      |\
			 BRx_MS_SDRAM_P                 |\
			 BRx_V)

#define CONFIG_SYS_OR2_PRELIM	 CONFIG_SYS_OR2_8COL

#define CONFIG_SYS_PSDMR	 CONFIG_SYS_PSDMR_8COL
#endif /* CONFIG_SYS_RAMBOOT */

#define CONFIG_SYS_BR4_PRELIM  ((RTC_BASE_ADDR & BRx_BA_MSK)   |\
			 BRx_PS_8                       |\
			 BRx_MS_UPMA                    |\
			 BRx_V)

#define CONFIG_SYS_OR4_PRELIM  (ORxU_AM_MSK | ORxU_BI)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_I82365

#define CONFIG_SYS_PCMCIA_MEM_ADDR	0x81000000
#define CONFIG_SYS_PCMCIA_MEM_SIZE	0x1000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	0xa0000000

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	0x100

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	0x100

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x108

#endif	/* __CONFIG_H */
Commit	Line	Data
7aa78614 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
7aa78614 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
	21	#define CONFIG_ATC 1 /* ...on a ATC board */
9c4c5ae3	22	#define CONFIG_CPM2 1 /* Has a CPM2 */
7aa78614	23
2ae18241 WD	24	#define CONFIG_SYS_TEXT_BASE 0xFF000000
2ae18241 WD	25
7aa78614 WD	26	/*
	27	* select serial console configuration
	28	*
	29	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	30	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	31	* for SCC).
	32	*
	33	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	34	* defined elsewhere (for example, on the cogent platform, there are serial
	35	* ports on the motherboard which are used for the serial console - see
	36	* cogent/cma101/serial.[ch]).
	37	*/
	38	#define CONFIG_CONS_ON_SMC /* define if console on SMC */
	39	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
	40	#undef CONFIG_CONS_NONE /* define if console on something else*/
	41	#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
	42
	43	#define CONFIG_BAUDRATE 115200
	44
	45	/*
	46	* select ethernet configuration
	47	*
	48	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	49	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	50	* for FCC)
	51	*
	52	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7	53	* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
7aa78614 WD	54	*/
	55	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
	56	#undef CONFIG_ETHER_NONE /* define if ether on something else */
	57	#define CONFIG_ETHER_ON_FCC
	58
7aa78614 WD	59	#define CONFIG_ETHER_ON_FCC2
	60
	61	/*
	62	* - Rx-CLK is CLK13
	63	* - Tx-CLK is CLK14
	64	* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
	65	* - Enable Full Duplex in FSMR
	66	*/
6d0f6bcf JCPV	67	# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2\|CMXFCR_RF2CS_MSK\|CMXFCR_TF2CS_MSK)
	68	# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13\|CMXFCR_TF2CS_CLK14)
	69	# define CONFIG_SYS_CPMFCR_RAMTYPE 0
	70	# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE\|FCC_PSMR_LPB)
7aa78614 WD	71
	72	#define CONFIG_ETHER_ON_FCC3
	73
	74	/*
	75	* - Rx-CLK is CLK15
	76	* - Tx-CLK is CLK16
	77	* - RAM for BD/Buffers is on the local Bus (see 28-13)
	78	* - Enable Half Duplex in FSMR
	79	*/
6d0f6bcf JCPV	80	# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3\|CMXFCR_RF3CS_MSK\|CMXFCR_TF3CS_MSK)
6d0f6bcf JCPV	81	# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15\|CMXFCR_TF3CS_CLK16)
7aa78614 WD	82
	83	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
	84	#define CONFIG_8260_CLKIN 64000000 /* in Hz */
	85
	86	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	87
	88	#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
	89
	90	#define CONFIG_PREBOOT \
	91	"echo;" \
32bf3d14	92	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
7aa78614 WD	93	"echo"
	94
	95	#undef CONFIG_BOOTARGS
	96	#define CONFIG_BOOTCOMMAND \
	97	"bootp;" \
	98	"setenv bootargs root=/dev/nfs rw " \
53677ef1	99	"nfsroot=${serverip}:${rootpath} " \
fe126d8b	100	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
7aa78614 WD	101	"bootm"
	102
	103	/*-----------------------------------------------------------------------
	104	* Miscellaneous configuration options
	105	*/
	106
	107	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	108	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
7aa78614	109
2fd90ce5 JL	110
	111	/*
	112	* BOOTP options
	113	*/
	114	#define CONFIG_BOOTP_SUBNETMASK
	115	#define CONFIG_BOOTP_GATEWAY
	116	#define CONFIG_BOOTP_HOSTNAME
	117	#define CONFIG_BOOTP_BOOTPATH
	118	#define CONFIG_BOOTP_BOOTFILESIZE
7aa78614	119
15ef8a5d	120
0b361c91 JL	121	/*
	122	* Command line configuration.
	123	*/
	124	#include <config_cmd_default.h>
15ef8a5d	125
0b361c91 JL	126	#define CONFIG_CMD_EEPROM
	127	#define CONFIG_CMD_PCI
	128	#define CONFIG_CMD_PCMCIA
	129	#define CONFIG_CMD_DATE
	130	#define CONFIG_CMD_IDE
7aa78614	131
0b361c91 JL	132
0b361c91 JL	133	#define CONFIG_DOS_PARTITION
7aa78614 WD	134
	135	/*
	136	* Miscellaneous configurable options
	137	*/
6d0f6bcf JCPV	138	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	139	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
0b361c91	140	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	141	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
7aa78614	142	#else
6d0f6bcf	143	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
7aa78614	144	#endif
6d0f6bcf JCPV	145	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	146	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	147	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
7aa78614	148
6d0f6bcf JCPV	149	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	150	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
7aa78614	151
6d0f6bcf	152	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
7aa78614	153
6d0f6bcf	154	#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
66fd3d1c	155
6d0f6bcf	156	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
7aa78614	157
6d0f6bcf	158	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
7aa78614	159
6d0f6bcf	160	#define CONFIG_SYS_ALLOC_DPRAM
7aa78614 WD	161
	162	#undef CONFIG_WATCHDOG /* watchdog disabled */
	163
	164	#define CONFIG_SPI
	165
15ef8a5d WD	166	#define CONFIG_RTC_DS12887
15ef8a5d WD	167
53677ef1 WD	168	#define RTC_BASE_ADDR 0xF5000000
	169	#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
	170	#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
15ef8a5d WD	171
	172	#define CONFIG_MISC_INIT_R
	173
7aa78614 WD	174	/*
	175	* For booting Linux, the board info and command line data
	176	* have to be in the first 8 MB of memory, since this is
	177	* the maximum mapped by the Linux kernel during initialization.
	178	*/
6d0f6bcf	179	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
7aa78614 WD	180
	181	/*-----------------------------------------------------------------------
	182	* Flash configuration
	183	*/
	184
6d0f6bcf JCPV	185	#define CONFIG_SYS_FLASH_BASE 0xFF000000
6d0f6bcf JCPV	186	#define CONFIG_SYS_FLASH_SIZE 0x00800000
7aa78614 WD	187
	188	/*-----------------------------------------------------------------------
	189	* FLASH organization
	190	*/
6d0f6bcf JCPV	191	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
6d0f6bcf JCPV	192	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
7aa78614	193
6d0f6bcf JCPV	194	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	195	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
7aa78614 WD	196
	197	#define CONFIG_FLASH_16BIT
	198
	199	/*-----------------------------------------------------------------------
	200	* Hard Reset Configuration Words
	201	*
6d0f6bcf	202	* if you change bits in the HRCW, you must also change the CONFIG_SYS_*
7aa78614	203	* defines for the various registers affected by the HRCW e.g. changing
6d0f6bcf	204	* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
7aa78614	205	*/
6d0f6bcf	206	#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP \| HRCW_ISB100 \| HRCW_BMS \| \
9a0e21a3	207	HRCW_BPS10 \|\
7aa78614 WD	208	HRCW_APPC10)
	209
	210	/* no slaves so just fill with zeros */
6d0f6bcf JCPV	211	#define CONFIG_SYS_HRCW_SLAVE1 0
	212	#define CONFIG_SYS_HRCW_SLAVE2 0
	213	#define CONFIG_SYS_HRCW_SLAVE3 0
	214	#define CONFIG_SYS_HRCW_SLAVE4 0
	215	#define CONFIG_SYS_HRCW_SLAVE5 0
	216	#define CONFIG_SYS_HRCW_SLAVE6 0
	217	#define CONFIG_SYS_HRCW_SLAVE7 0
7aa78614 WD	218
	219	/*-----------------------------------------------------------------------
	220	* Internal Memory Mapped Register
	221	*/
6d0f6bcf	222	#define CONFIG_SYS_IMMR 0xF0000000
7aa78614 WD	223
	224	/*-----------------------------------------------------------------------
	225	* Definitions for initial stack pointer and data area (in DPRAM)
	226	*/
6d0f6bcf	227	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	228	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	229	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	230	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
7aa78614 WD	231
	232	/*-----------------------------------------------------------------------
	233	* Start addresses for the final memory configuration
	234	* (Set up by the startup code)
6d0f6bcf	235	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
7aa78614	236	*
6d0f6bcf	237	* 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
7aa78614	238	*/
6d0f6bcf JCPV	239	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	240	#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
14d0a02a	241	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	242	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
6d0f6bcf JCPV	243	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
7aa78614	244
6d0f6bcf JCPV	245	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	246	# define CONFIG_SYS_RAMBOOT
7aa78614 WD	247	#endif
7aa78614 WD	248
66fd3d1c	249	#define CONFIG_PCI
842033e6	250	#define CONFIG_PCI_INDIRECT_BRIDGE
66fd3d1c	251	#define CONFIG_PCI_PNP
6d0f6bcf	252	#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
66fd3d1c	253
7aa78614 WD	254	#if 1
7aa78614 WD	255	/* environment is in Flash */
5a1aceb0	256	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	257	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x30000)
0e8d1586 JCPV	258	# define CONFIG_ENV_SIZE 0x10000
0e8d1586 JCPV	259	# define CONFIG_ENV_SECT_SIZE 0x10000
7aa78614	260	#else
bb1f8b4f	261	#define CONFIG_ENV_IS_IN_EEPROM 1
0e8d1586 JCPV	262	#define CONFIG_ENV_OFFSET 0
0e8d1586 JCPV	263	#define CONFIG_ENV_SIZE 2048
6d0f6bcf	264	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
7aa78614	265	#endif
7aa78614 WD	266
	267	/*-----------------------------------------------------------------------
	268	* Cache Configuration
	269	*/
6d0f6bcf	270	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
0b361c91	271	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	272	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
7aa78614 WD	273	#endif
	274
	275	/*-----------------------------------------------------------------------
	276	* HIDx - Hardware Implementation-dependent Registers 2-11
	277	*-----------------------------------------------------------------------
	278	* HID0 also contains cache control - initially enable both caches and
	279	* invalidate contents, then the final state leaves only the instruction
	280	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
	281	* but Soft reset does not.
	282	*
	283	* HID1 has only read-only information - nothing to set.
	284	*/
6d0f6bcf	285	#define CONFIG_SYS_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|\
8bde7f77	286	HID0_DCI\|HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	287	#define CONFIG_SYS_HID0_FINAL (HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	288	#define CONFIG_SYS_HID2 0
7aa78614 WD	289
	290	/*-----------------------------------------------------------------------
	291	* RMR - Reset Mode Register 5-5
	292	*-----------------------------------------------------------------------
	293	* turn on Checkstop Reset Enable
	294	*/
6d0f6bcf	295	#define CONFIG_SYS_RMR RMR_CSRE
7aa78614 WD	296
	297	/*-----------------------------------------------------------------------
	298	* BCR - Bus Configuration 4-25
	299	*-----------------------------------------------------------------------
	300	*/
	301	#define BCR_APD01 0x10000000
6d0f6bcf	302	#define CONFIG_SYS_BCR (BCR_APD01\|BCR_ETM\|BCR_LETM) /* 8260 mode */
7aa78614 WD	303
	304	/*-----------------------------------------------------------------------
	305	* SIUMCR - SIU Module Configuration 4-31
	306	*-----------------------------------------------------------------------
	307	*/
6d0f6bcf	308	#define CONFIG_SYS_SIUMCR (SIUMCR_BBD\|SIUMCR_APPC10\|\
7aa78614 WD	309	SIUMCR_CS10PC00\|SIUMCR_BCTLC10)
	310
	311	/*-----------------------------------------------------------------------
	312	* SYPCR - System Protection Control 4-35
	313	* SYPCR can only be written once after reset!
	314	*-----------------------------------------------------------------------
	315	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	316	*/
	317	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	318	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
8bde7f77	319	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
7aa78614	320	#else
6d0f6bcf	321	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
8bde7f77	322	SYPCR_SWRI\|SYPCR_SWP)
7aa78614 WD	323	#endif /* CONFIG_WATCHDOG */
	324
	325	/*-----------------------------------------------------------------------
	326	* TMCNTSC - Time Counter Status and Control 4-40
	327	*-----------------------------------------------------------------------
	328	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	329	* and enable Time Counter
	330	*/
6d0f6bcf	331	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
7aa78614 WD	332
	333	/*-----------------------------------------------------------------------
	334	* PISCR - Periodic Interrupt Status and Control 4-42
	335	*-----------------------------------------------------------------------
	336	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	337	* Periodic timer
	338	*/
6d0f6bcf	339	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
7aa78614 WD	340
	341	/*-----------------------------------------------------------------------
	342	* SCCR - System Clock Control 9-8
	343	*-----------------------------------------------------------------------
	344	* Ensure DFBRG is Divide by 16
	345	*/
6d0f6bcf	346	#define CONFIG_SYS_SCCR SCCR_DFBRG01
7aa78614 WD	347
	348	/*-----------------------------------------------------------------------
	349	* RCCR - RISC Controller Configuration 13-7
	350	*-----------------------------------------------------------------------
	351	*/
6d0f6bcf	352	#define CONFIG_SYS_RCCR 0
7aa78614	353
6d0f6bcf	354	#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
7aa78614 WD	355	/*-----------------------------------------------------------------------
	356	* MPTPR - Memory Refresh Timer Prescaler Register 10-18
	357	*-----------------------------------------------------------------------
	358	*/
6d0f6bcf	359	#define CONFIG_SYS_MPTPR 0x1F00
7aa78614 WD	360
	361	/*-----------------------------------------------------------------------
	362	* PSRT - Refresh Timer Register 10-16
	363	*-----------------------------------------------------------------------
	364	*/
6d0f6bcf	365	#define CONFIG_SYS_PSRT 0x0f
7aa78614 WD	366
	367	/*-----------------------------------------------------------------------
	368	* PSRT - SDRAM Mode Register 10-10
	369	*-----------------------------------------------------------------------
	370	*/
	371
	372	/* SDRAM initialization values for 8-column chips
	373	*/
6d0f6bcf	374	#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK \|\
7aa78614	375	ORxS_BPD_4 \|\
f7de16ae WD	376	ORxS_ROWST_PBI1_A7 \|\
f7de16ae WD	377	ORxS_NUMR_12)
7aa78614	378
6d0f6bcf	379	#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI \|\
f7de16ae WD	380	PSDMR_SDAM_A15_IS_A5 \|\
	381	PSDMR_BSMA_A15_A17 \|\
	382	PSDMR_SDA10_PBI1_A7 \|\
7aa78614	383	PSDMR_RFRC_7_CLK \|\
f7de16ae WD	384	PSDMR_PRETOACT_3W \|\
f7de16ae WD	385	PSDMR_ACTTORW_2W \|\
7aa78614 WD	386	PSDMR_LDOTOPRE_1C \|\
	387	PSDMR_WRC_1C \|\
	388	PSDMR_CL_2)
	389
	390	/* SDRAM initialization values for 9-column chips
	391	*/
6d0f6bcf	392	#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK \|\
7aa78614	393	ORxS_BPD_4 \|\
f7de16ae WD	394	ORxS_ROWST_PBI1_A6 \|\
f7de16ae WD	395	ORxS_NUMR_12)
7aa78614	396
6d0f6bcf	397	#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI \|\
f7de16ae WD	398	PSDMR_SDAM_A16_IS_A5 \|\
	399	PSDMR_BSMA_A15_A17 \|\
	400	PSDMR_SDA10_PBI1_A6 \|\
7aa78614	401	PSDMR_RFRC_7_CLK \|\
f7de16ae WD	402	PSDMR_PRETOACT_3W \|\
f7de16ae WD	403	PSDMR_ACTTORW_2W \|\
7aa78614 WD	404	PSDMR_LDOTOPRE_1C \|\
	405	PSDMR_WRC_1C \|\
	406	PSDMR_CL_2)
	407
	408	/*
	409	* Init Memory Controller:
	410	*
	411	* Bank Bus Machine PortSz Device
	412	* ---- --- ------- ------ ------
	413	* 0 60x GPCM 8 bit Boot ROM
	414	* 1 60x GPCM 64 bit FLASH
	415	* 2 60x SDRAM 64 bit SDRAM
	416	*
	417	*/
	418
6d0f6bcf	419	#define CONFIG_SYS_MRS_OFFS 0x00000000
7aa78614 WD	420
	421	/* Bank 0 - FLASH
	422	*/
6d0f6bcf	423	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	424	BRx_PS_16 \|\
	425	BRx_MS_GPCM_P \|\
	426	BRx_V)
7aa78614	427
6d0f6bcf	428	#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) \|\
8bde7f77 WD	429	ORxG_CSNT \|\
	430	ORxG_ACS_DIV1 \|\
	431	ORxG_SCY_3_CLK \|\
	432	ORxU_EHTR_8IDLE)
7aa78614 WD	433
	434
	435	/* Bank 2 - 60x bus SDRAM
	436	*/
6d0f6bcf JCPV	437	#ifndef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	438	#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	439	BRx_PS_64 \|\
	440	BRx_MS_SDRAM_P \|\
	441	BRx_V)
7aa78614	442
6d0f6bcf	443	#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
7aa78614	444
6d0f6bcf JCPV	445	#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL
6d0f6bcf JCPV	446	#endif /* CONFIG_SYS_RAMBOOT */
7aa78614	447
6d0f6bcf	448	#define CONFIG_SYS_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) \|\
8bde7f77 WD	449	BRx_PS_8 \|\
	450	BRx_MS_UPMA \|\
	451	BRx_V)
15ef8a5d	452
6d0f6bcf	453	#define CONFIG_SYS_OR4_PRELIM (ORxU_AM_MSK \| ORxU_BI)
8bde7f77	454
66fd3d1c WD	455	/*-----------------------------------------------------------------------
	456	* PCMCIA stuff
	457	*-----------------------------------------------------------------------
	458	*
	459	*/
	460	#define CONFIG_I82365
	461
6d0f6bcf JCPV	462	#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x81000000
6d0f6bcf JCPV	463	#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000
66fd3d1c WD	464
	465	/*-----------------------------------------------------------------------
	466	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	467	*-----------------------------------------------------------------------
	468	*/
	469
8d1165e1	470	#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
66fd3d1c WD	471	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	472
	473	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	474	#undef CONFIG_IDE_LED /* LED for ide not supported */
	475	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	476
6d0f6bcf JCPV	477	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	478	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
66fd3d1c	479
6d0f6bcf	480	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
66fd3d1c	481
6d0f6bcf	482	#define CONFIG_SYS_ATA_BASE_ADDR 0xa0000000
66fd3d1c WD	483
66fd3d1c WD	484	/* Offset for data I/O */
6d0f6bcf	485	#define CONFIG_SYS_ATA_DATA_OFFSET 0x100
66fd3d1c WD	486
66fd3d1c WD	487	/* Offset for normal register accesses */
6d0f6bcf	488	#define CONFIG_SYS_ATA_REG_OFFSET 0x100
66fd3d1c WD	489
66fd3d1c WD	490	/* Offset for alternate registers */
6d0f6bcf	491	#define CONFIG_SYS_ATA_ALT_OFFSET 0x108
66fd3d1c	492
7aa78614	493	#endif /* __CONFIG_H */