[people/ms/u-boot.git] / include / configs / atc.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
#define CONFIG_ATC		1	/* ...on a ATC board	*/
#define CONFIG_CPM2		1	/* Has a CPM2 */

#define	CONFIG_SYS_TEXT_BASE	0xFF000000

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#define  CONFIG_CONS_ON_SMC		/* define if console on SMC */
#undef CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef  CONFIG_CONS_NONE		/* define if console on something else*/
#define CONFIG_CONS_INDEX	2	/* which serial channel for console */

#define CONFIG_BAUDRATE		115200

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 */
#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
#define CONFIG_ETHER_ON_FCC

#define CONFIG_ETHER_ON_FCC2

/*
 * - Rx-CLK is CLK13
 * - Tx-CLK is CLK14
 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 * - Enable Full Duplex in FSMR
 */
# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
# define CONFIG_SYS_CPMFCR_RAMTYPE	0
# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)

#define CONFIG_ETHER_ON_FCC3

/*
 * - Rx-CLK is CLK15
 * - Tx-CLK is CLK16
 * - RAM for BD/Buffers is on the local Bus (see 28-13)
 * - Enable Half Duplex in FSMR
 */
# define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
# define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)

/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	64000000	/* in Hz */

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#undef	CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in Hz */

#define CONFIG_PREBOOT							\
	"echo;"								\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
	"echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND						\
	"bootp;"							\
	"setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=${serverip}:${rootpath} "				\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
	"bootm"

/*-----------------------------------------------------------------------
 * Miscellaneous configuration options
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_DATE
#define CONFIG_CMD_IDE


#define CONFIG_DOS_PARTITION

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/

#define CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define	CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/

#define CONFIG_SYS_ALLOC_DPRAM

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SPI

#define CONFIG_RTC_DS12887

#define RTC_BASE_ADDR		0xF5000000
#define RTC_PORT_ADDR		RTC_BASE_ADDR + 0x800
#define RTC_PORT_DATA		RTC_BASE_ADDR + 0x808

#define CONFIG_MISC_INIT_R

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * Flash configuration
 */

#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_FLASH_SIZE		0x00800000

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#define CONFIG_FLASH_16BIT

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 */
#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
				 HRCW_BPS10 |\
				 HRCW_APPC10)

/* no slaves so just fill with zeros */
#define CONFIG_SYS_HRCW_SLAVE1		0
#define CONFIG_SYS_HRCW_SLAVE2		0
#define CONFIG_SYS_HRCW_SLAVE3		0
#define CONFIG_SYS_HRCW_SLAVE4		0
#define CONFIG_SYS_HRCW_SLAVE5		0
#define CONFIG_SYS_HRCW_SLAVE6		0
#define CONFIG_SYS_HRCW_SLAVE7		0

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00  /* Size of used area in DPRAM    */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 *
 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT
#endif

#define	CONFIG_PCI
#define	CONFIG_PCI_PNP
#define	CONFIG_SYS_PCI_MSTR_IO_BUS	0x00000000	/* PCI base   */

#if 1
/* environment is in Flash */
#define CONFIG_ENV_IS_IN_FLASH	1
# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x30000)
# define CONFIG_ENV_SIZE		0x10000
# define CONFIG_ENV_SECT_SIZE	0x10000
#else
#define CONFIG_ENV_IS_IN_EEPROM	1
#define CONFIG_ENV_OFFSET		0
#define CONFIG_ENV_SIZE		2048
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 16-byte page size	*/
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers                    2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
			 HID0_DCI|HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
#define CONFIG_SYS_HID2        0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register                                     5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CONFIG_SYS_RMR         RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration                                       4-25
 *-----------------------------------------------------------------------
 */
#define BCR_APD01	0x10000000
#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration                             4-31
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_APPC10|\
			 SIUMCR_CS10PC00|SIUMCR_BCTLC10)

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control                             4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control                     4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control                 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control                                   9-8
 *-----------------------------------------------------------------------
 * Ensure DFBRG is Divide by 16
 */
#define CONFIG_SYS_SCCR        SCCR_DFBRG01

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration                         13-7
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RCCR        0

#define CONFIG_SYS_MIN_AM_MASK	0xC0000000
/*-----------------------------------------------------------------------
 * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_MPTPR       0x1F00

/*-----------------------------------------------------------------------
 * PSRT - Refresh Timer Register                                10-16
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_PSRT        0x0f

/*-----------------------------------------------------------------------
 * PSRT - SDRAM Mode Register                                   10-10
 *-----------------------------------------------------------------------
 */

	/* SDRAM initialization values for 8-column chips
	 */
#define CONFIG_SYS_OR2_8COL	(CONFIG_SYS_MIN_AM_MASK		|\
			 ORxS_BPD_4			|\
			 ORxS_ROWST_PBI1_A7		|\
			 ORxS_NUMR_12)

#define CONFIG_SYS_PSDMR_8COL	(PSDMR_PBI			|\
			 PSDMR_SDAM_A15_IS_A5		|\
			 PSDMR_BSMA_A15_A17		|\
			 PSDMR_SDA10_PBI1_A7		|\
			 PSDMR_RFRC_7_CLK		|\
			 PSDMR_PRETOACT_3W		|\
			 PSDMR_ACTTORW_2W		|\
			 PSDMR_LDOTOPRE_1C		|\
			 PSDMR_WRC_1C			|\
			 PSDMR_CL_2)

	/* SDRAM initialization values for 9-column chips
	 */
#define CONFIG_SYS_OR2_9COL	(CONFIG_SYS_MIN_AM_MASK		|\
			 ORxS_BPD_4			|\
			 ORxS_ROWST_PBI1_A6		|\
			 ORxS_NUMR_12)

#define CONFIG_SYS_PSDMR_9COL	(PSDMR_PBI			|\
			 PSDMR_SDAM_A16_IS_A5		|\
			 PSDMR_BSMA_A15_A17		|\
			 PSDMR_SDA10_PBI1_A6		|\
			 PSDMR_RFRC_7_CLK		|\
			 PSDMR_PRETOACT_3W		|\
			 PSDMR_ACTTORW_2W		|\
			 PSDMR_LDOTOPRE_1C		|\
			 PSDMR_WRC_1C			|\
			 PSDMR_CL_2)

/*
 * Init Memory Controller:
 *
 * Bank Bus     Machine PortSz  Device
 * ---- ---     ------- ------  ------
 *  0   60x     GPCM    8  bit  Boot ROM
 *  1   60x     GPCM    64 bit  FLASH
 *  2   60x     SDRAM   64 bit  SDRAM
 *
 */

#define CONFIG_SYS_MRS_OFFS	0x00000000

/* Bank 0 - FLASH
 */
#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
			 BRx_PS_16                      |\
			 BRx_MS_GPCM_P                  |\
			 BRx_V)

#define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
			 ORxG_CSNT                      |\
			 ORxG_ACS_DIV1                  |\
			 ORxG_SCY_3_CLK                 |\
			 ORxU_EHTR_8IDLE)


/* Bank 2 - 60x bus SDRAM
 */
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
			 BRx_PS_64                      |\
			 BRx_MS_SDRAM_P                 |\
			 BRx_V)

#define CONFIG_SYS_OR2_PRELIM	 CONFIG_SYS_OR2_8COL

#define CONFIG_SYS_PSDMR	 CONFIG_SYS_PSDMR_8COL
#endif /* CONFIG_SYS_RAMBOOT */

#define CONFIG_SYS_BR4_PRELIM  ((RTC_BASE_ADDR & BRx_BA_MSK)   |\
			 BRx_PS_8                       |\
			 BRx_MS_UPMA                    |\
			 BRx_V)

#define CONFIG_SYS_OR4_PRELIM  (ORxU_AM_MSK | ORxU_BI)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_I82365

#define CONFIG_SYS_PCMCIA_MEM_ADDR	0x81000000
#define CONFIG_SYS_PCMCIA_MEM_SIZE	0x1000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	0xa0000000

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	0x100

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	0x100

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x108

#endif	/* __CONFIG_H */
Commit	Line	Data
7aa78614 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
	37	#define CONFIG_ATC 1 /* ...on a ATC board */
9c4c5ae3	38	#define CONFIG_CPM2 1 /* Has a CPM2 */
7aa78614	39
2ae18241 WD	40	#define CONFIG_SYS_TEXT_BASE 0xFF000000
2ae18241 WD	41
7aa78614 WD	42	/*
	43	* select serial console configuration
	44	*
	45	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	46	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	47	* for SCC).
	48	*
	49	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	50	* defined elsewhere (for example, on the cogent platform, there are serial
	51	* ports on the motherboard which are used for the serial console - see
	52	* cogent/cma101/serial.[ch]).
	53	*/
	54	#define CONFIG_CONS_ON_SMC /* define if console on SMC */
	55	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
	56	#undef CONFIG_CONS_NONE /* define if console on something else*/
	57	#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
	58
	59	#define CONFIG_BAUDRATE 115200
	60
	61	/*
	62	* select ethernet configuration
	63	*
	64	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	65	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	66	* for FCC)
	67	*
	68	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7	69	* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
7aa78614 WD	70	*/
	71	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
	72	#undef CONFIG_ETHER_NONE /* define if ether on something else */
	73	#define CONFIG_ETHER_ON_FCC
	74
7aa78614 WD	75	#define CONFIG_ETHER_ON_FCC2
	76
	77	/*
	78	* - Rx-CLK is CLK13
	79	* - Tx-CLK is CLK14
	80	* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
	81	* - Enable Full Duplex in FSMR
	82	*/
6d0f6bcf JCPV	83	# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2\|CMXFCR_RF2CS_MSK\|CMXFCR_TF2CS_MSK)
	84	# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13\|CMXFCR_TF2CS_CLK14)
	85	# define CONFIG_SYS_CPMFCR_RAMTYPE 0
	86	# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE\|FCC_PSMR_LPB)
7aa78614 WD	87
	88	#define CONFIG_ETHER_ON_FCC3
	89
	90	/*
	91	* - Rx-CLK is CLK15
	92	* - Tx-CLK is CLK16
	93	* - RAM for BD/Buffers is on the local Bus (see 28-13)
	94	* - Enable Half Duplex in FSMR
	95	*/
6d0f6bcf JCPV	96	# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3\|CMXFCR_RF3CS_MSK\|CMXFCR_TF3CS_MSK)
6d0f6bcf JCPV	97	# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15\|CMXFCR_TF3CS_CLK16)
7aa78614 WD	98
	99	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
	100	#define CONFIG_8260_CLKIN 64000000 /* in Hz */
	101
	102	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	103
	104	#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
	105
	106	#define CONFIG_PREBOOT \
	107	"echo;" \
32bf3d14	108	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
7aa78614 WD	109	"echo"
	110
	111	#undef CONFIG_BOOTARGS
	112	#define CONFIG_BOOTCOMMAND \
	113	"bootp;" \
	114	"setenv bootargs root=/dev/nfs rw " \
53677ef1	115	"nfsroot=${serverip}:${rootpath} " \
fe126d8b	116	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
7aa78614 WD	117	"bootm"
	118
	119	/*-----------------------------------------------------------------------
	120	* Miscellaneous configuration options
	121	*/
	122
	123	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	124	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
7aa78614	125
2fd90ce5 JL	126
	127	/*
	128	* BOOTP options
	129	*/
	130	#define CONFIG_BOOTP_SUBNETMASK
	131	#define CONFIG_BOOTP_GATEWAY
	132	#define CONFIG_BOOTP_HOSTNAME
	133	#define CONFIG_BOOTP_BOOTPATH
	134	#define CONFIG_BOOTP_BOOTFILESIZE
7aa78614	135
15ef8a5d	136
0b361c91 JL	137	/*
	138	* Command line configuration.
	139	*/
	140	#include <config_cmd_default.h>
15ef8a5d	141
0b361c91 JL	142	#define CONFIG_CMD_EEPROM
	143	#define CONFIG_CMD_PCI
	144	#define CONFIG_CMD_PCMCIA
	145	#define CONFIG_CMD_DATE
	146	#define CONFIG_CMD_IDE
7aa78614	147
0b361c91 JL	148
0b361c91 JL	149	#define CONFIG_DOS_PARTITION
7aa78614 WD	150
	151	/*
	152	* Miscellaneous configurable options
	153	*/
6d0f6bcf JCPV	154	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	155	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
0b361c91	156	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	157	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
7aa78614	158	#else
6d0f6bcf	159	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
7aa78614	160	#endif
6d0f6bcf JCPV	161	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	162	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	163	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
7aa78614	164
6d0f6bcf JCPV	165	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	166	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
7aa78614	167
6d0f6bcf	168	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
7aa78614	169
6d0f6bcf	170	#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
66fd3d1c	171
6d0f6bcf	172	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
7aa78614	173
6d0f6bcf	174	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
7aa78614	175
6d0f6bcf	176	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
7aa78614	177
6d0f6bcf	178	#define CONFIG_SYS_ALLOC_DPRAM
7aa78614 WD	179
	180	#undef CONFIG_WATCHDOG /* watchdog disabled */
	181
	182	#define CONFIG_SPI
	183
15ef8a5d WD	184	#define CONFIG_RTC_DS12887
15ef8a5d WD	185
53677ef1 WD	186	#define RTC_BASE_ADDR 0xF5000000
	187	#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
	188	#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
15ef8a5d WD	189
	190	#define CONFIG_MISC_INIT_R
	191
7aa78614 WD	192	/*
	193	* For booting Linux, the board info and command line data
	194	* have to be in the first 8 MB of memory, since this is
	195	* the maximum mapped by the Linux kernel during initialization.
	196	*/
6d0f6bcf	197	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
7aa78614 WD	198
	199	/*-----------------------------------------------------------------------
	200	* Flash configuration
	201	*/
	202
6d0f6bcf JCPV	203	#define CONFIG_SYS_FLASH_BASE 0xFF000000
6d0f6bcf JCPV	204	#define CONFIG_SYS_FLASH_SIZE 0x00800000
7aa78614 WD	205
	206	/*-----------------------------------------------------------------------
	207	* FLASH organization
	208	*/
6d0f6bcf JCPV	209	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
6d0f6bcf JCPV	210	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
7aa78614	211
6d0f6bcf JCPV	212	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	213	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
7aa78614 WD	214
	215	#define CONFIG_FLASH_16BIT
	216
	217	/*-----------------------------------------------------------------------
	218	* Hard Reset Configuration Words
	219	*
6d0f6bcf	220	* if you change bits in the HRCW, you must also change the CONFIG_SYS_*
7aa78614	221	* defines for the various registers affected by the HRCW e.g. changing
6d0f6bcf	222	* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
7aa78614	223	*/
6d0f6bcf	224	#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP \| HRCW_ISB100 \| HRCW_BMS \| \
9a0e21a3	225	HRCW_BPS10 \|\
7aa78614 WD	226	HRCW_APPC10)
	227
	228	/* no slaves so just fill with zeros */
6d0f6bcf JCPV	229	#define CONFIG_SYS_HRCW_SLAVE1 0
	230	#define CONFIG_SYS_HRCW_SLAVE2 0
	231	#define CONFIG_SYS_HRCW_SLAVE3 0
	232	#define CONFIG_SYS_HRCW_SLAVE4 0
	233	#define CONFIG_SYS_HRCW_SLAVE5 0
	234	#define CONFIG_SYS_HRCW_SLAVE6 0
	235	#define CONFIG_SYS_HRCW_SLAVE7 0
7aa78614 WD	236
	237	/*-----------------------------------------------------------------------
	238	* Internal Memory Mapped Register
	239	*/
6d0f6bcf	240	#define CONFIG_SYS_IMMR 0xF0000000
7aa78614 WD	241
	242	/*-----------------------------------------------------------------------
	243	* Definitions for initial stack pointer and data area (in DPRAM)
	244	*/
6d0f6bcf	245	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	246	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	247	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	248	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
7aa78614 WD	249
	250	/*-----------------------------------------------------------------------
	251	* Start addresses for the final memory configuration
	252	* (Set up by the startup code)
6d0f6bcf	253	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
7aa78614	254	*
6d0f6bcf	255	* 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
7aa78614	256	*/
6d0f6bcf JCPV	257	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	258	#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
14d0a02a	259	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	260	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
6d0f6bcf JCPV	261	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
7aa78614	262
6d0f6bcf JCPV	263	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	264	# define CONFIG_SYS_RAMBOOT
7aa78614 WD	265	#endif
7aa78614 WD	266
66fd3d1c WD	267	#define CONFIG_PCI
66fd3d1c WD	268	#define CONFIG_PCI_PNP
6d0f6bcf	269	#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
66fd3d1c	270
7aa78614 WD	271	#if 1
7aa78614 WD	272	/* environment is in Flash */
5a1aceb0	273	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	274	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x30000)
0e8d1586 JCPV	275	# define CONFIG_ENV_SIZE 0x10000
0e8d1586 JCPV	276	# define CONFIG_ENV_SECT_SIZE 0x10000
7aa78614	277	#else
bb1f8b4f	278	#define CONFIG_ENV_IS_IN_EEPROM 1
0e8d1586 JCPV	279	#define CONFIG_ENV_OFFSET 0
0e8d1586 JCPV	280	#define CONFIG_ENV_SIZE 2048
6d0f6bcf	281	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
7aa78614	282	#endif
7aa78614 WD	283
	284	/*-----------------------------------------------------------------------
	285	* Cache Configuration
	286	*/
6d0f6bcf	287	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
0b361c91	288	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	289	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
7aa78614 WD	290	#endif
	291
	292	/*-----------------------------------------------------------------------
	293	* HIDx - Hardware Implementation-dependent Registers 2-11
	294	*-----------------------------------------------------------------------
	295	* HID0 also contains cache control - initially enable both caches and
	296	* invalidate contents, then the final state leaves only the instruction
	297	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
	298	* but Soft reset does not.
	299	*
	300	* HID1 has only read-only information - nothing to set.
	301	*/
6d0f6bcf	302	#define CONFIG_SYS_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|\
8bde7f77	303	HID0_DCI\|HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	304	#define CONFIG_SYS_HID0_FINAL (HID0_IFEM\|HID0_ABE)
6d0f6bcf JCPV	305	#define CONFIG_SYS_HID2 0
7aa78614 WD	306
	307	/*-----------------------------------------------------------------------
	308	* RMR - Reset Mode Register 5-5
	309	*-----------------------------------------------------------------------
	310	* turn on Checkstop Reset Enable
	311	*/
6d0f6bcf	312	#define CONFIG_SYS_RMR RMR_CSRE
7aa78614 WD	313
	314	/*-----------------------------------------------------------------------
	315	* BCR - Bus Configuration 4-25
	316	*-----------------------------------------------------------------------
	317	*/
	318	#define BCR_APD01 0x10000000
6d0f6bcf	319	#define CONFIG_SYS_BCR (BCR_APD01\|BCR_ETM\|BCR_LETM) /* 8260 mode */
7aa78614 WD	320
	321	/*-----------------------------------------------------------------------
	322	* SIUMCR - SIU Module Configuration 4-31
	323	*-----------------------------------------------------------------------
	324	*/
6d0f6bcf	325	#define CONFIG_SYS_SIUMCR (SIUMCR_BBD\|SIUMCR_APPC10\|\
7aa78614 WD	326	SIUMCR_CS10PC00\|SIUMCR_BCTLC10)
	327
	328	/*-----------------------------------------------------------------------
	329	* SYPCR - System Protection Control 4-35
	330	* SYPCR can only be written once after reset!
	331	*-----------------------------------------------------------------------
	332	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	333	*/
	334	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	335	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
8bde7f77	336	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
7aa78614	337	#else
6d0f6bcf	338	#define CONFIG_SYS_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
8bde7f77	339	SYPCR_SWRI\|SYPCR_SWP)
7aa78614 WD	340	#endif /* CONFIG_WATCHDOG */
	341
	342	/*-----------------------------------------------------------------------
	343	* TMCNTSC - Time Counter Status and Control 4-40
	344	*-----------------------------------------------------------------------
	345	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	346	* and enable Time Counter
	347	*/
6d0f6bcf	348	#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
7aa78614 WD	349
	350	/*-----------------------------------------------------------------------
	351	* PISCR - Periodic Interrupt Status and Control 4-42
	352	*-----------------------------------------------------------------------
	353	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	354	* Periodic timer
	355	*/
6d0f6bcf	356	#define CONFIG_SYS_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
7aa78614 WD	357
	358	/*-----------------------------------------------------------------------
	359	* SCCR - System Clock Control 9-8
	360	*-----------------------------------------------------------------------
	361	* Ensure DFBRG is Divide by 16
	362	*/
6d0f6bcf	363	#define CONFIG_SYS_SCCR SCCR_DFBRG01
7aa78614 WD	364
	365	/*-----------------------------------------------------------------------
	366	* RCCR - RISC Controller Configuration 13-7
	367	*-----------------------------------------------------------------------
	368	*/
6d0f6bcf	369	#define CONFIG_SYS_RCCR 0
7aa78614	370
6d0f6bcf	371	#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
7aa78614 WD	372	/*-----------------------------------------------------------------------
	373	* MPTPR - Memory Refresh Timer Prescaler Register 10-18
	374	*-----------------------------------------------------------------------
	375	*/
6d0f6bcf	376	#define CONFIG_SYS_MPTPR 0x1F00
7aa78614 WD	377
	378	/*-----------------------------------------------------------------------
	379	* PSRT - Refresh Timer Register 10-16
	380	*-----------------------------------------------------------------------
	381	*/
6d0f6bcf	382	#define CONFIG_SYS_PSRT 0x0f
7aa78614 WD	383
	384	/*-----------------------------------------------------------------------
	385	* PSRT - SDRAM Mode Register 10-10
	386	*-----------------------------------------------------------------------
	387	*/
	388
	389	/* SDRAM initialization values for 8-column chips
	390	*/
6d0f6bcf	391	#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK \|\
7aa78614	392	ORxS_BPD_4 \|\
f7de16ae WD	393	ORxS_ROWST_PBI1_A7 \|\
f7de16ae WD	394	ORxS_NUMR_12)
7aa78614	395
6d0f6bcf	396	#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI \|\
f7de16ae WD	397	PSDMR_SDAM_A15_IS_A5 \|\
	398	PSDMR_BSMA_A15_A17 \|\
	399	PSDMR_SDA10_PBI1_A7 \|\
7aa78614	400	PSDMR_RFRC_7_CLK \|\
f7de16ae WD	401	PSDMR_PRETOACT_3W \|\
f7de16ae WD	402	PSDMR_ACTTORW_2W \|\
7aa78614 WD	403	PSDMR_LDOTOPRE_1C \|\
	404	PSDMR_WRC_1C \|\
	405	PSDMR_CL_2)
	406
	407	/* SDRAM initialization values for 9-column chips
	408	*/
6d0f6bcf	409	#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK \|\
7aa78614	410	ORxS_BPD_4 \|\
f7de16ae WD	411	ORxS_ROWST_PBI1_A6 \|\
f7de16ae WD	412	ORxS_NUMR_12)
7aa78614	413
6d0f6bcf	414	#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI \|\
f7de16ae WD	415	PSDMR_SDAM_A16_IS_A5 \|\
	416	PSDMR_BSMA_A15_A17 \|\
	417	PSDMR_SDA10_PBI1_A6 \|\
7aa78614	418	PSDMR_RFRC_7_CLK \|\
f7de16ae WD	419	PSDMR_PRETOACT_3W \|\
f7de16ae WD	420	PSDMR_ACTTORW_2W \|\
7aa78614 WD	421	PSDMR_LDOTOPRE_1C \|\
	422	PSDMR_WRC_1C \|\
	423	PSDMR_CL_2)
	424
	425	/*
	426	* Init Memory Controller:
	427	*
	428	* Bank Bus Machine PortSz Device
	429	* ---- --- ------- ------ ------
	430	* 0 60x GPCM 8 bit Boot ROM
	431	* 1 60x GPCM 64 bit FLASH
	432	* 2 60x SDRAM 64 bit SDRAM
	433	*
	434	*/
	435
6d0f6bcf	436	#define CONFIG_SYS_MRS_OFFS 0x00000000
7aa78614 WD	437
	438	/* Bank 0 - FLASH
	439	*/
6d0f6bcf	440	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	441	BRx_PS_16 \|\
	442	BRx_MS_GPCM_P \|\
	443	BRx_V)
7aa78614	444
6d0f6bcf	445	#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) \|\
8bde7f77 WD	446	ORxG_CSNT \|\
	447	ORxG_ACS_DIV1 \|\
	448	ORxG_SCY_3_CLK \|\
	449	ORxU_EHTR_8IDLE)
7aa78614 WD	450
	451
	452	/* Bank 2 - 60x bus SDRAM
	453	*/
6d0f6bcf JCPV	454	#ifndef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	455	#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	456	BRx_PS_64 \|\
	457	BRx_MS_SDRAM_P \|\
	458	BRx_V)
7aa78614	459
6d0f6bcf	460	#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
7aa78614	461
6d0f6bcf JCPV	462	#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL
6d0f6bcf JCPV	463	#endif /* CONFIG_SYS_RAMBOOT */
7aa78614	464
6d0f6bcf	465	#define CONFIG_SYS_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) \|\
8bde7f77 WD	466	BRx_PS_8 \|\
	467	BRx_MS_UPMA \|\
	468	BRx_V)
15ef8a5d	469
6d0f6bcf	470	#define CONFIG_SYS_OR4_PRELIM (ORxU_AM_MSK \| ORxU_BI)
8bde7f77	471
66fd3d1c WD	472	/*-----------------------------------------------------------------------
	473	* PCMCIA stuff
	474	*-----------------------------------------------------------------------
	475	*
	476	*/
	477	#define CONFIG_I82365
	478
6d0f6bcf JCPV	479	#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x81000000
6d0f6bcf JCPV	480	#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000
66fd3d1c WD	481
	482	/*-----------------------------------------------------------------------
	483	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	484	*-----------------------------------------------------------------------
	485	*/
	486
	487	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	488
	489	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	490	#undef CONFIG_IDE_LED /* LED for ide not supported */
	491	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	492
6d0f6bcf JCPV	493	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	494	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
66fd3d1c	495
6d0f6bcf	496	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
66fd3d1c	497
6d0f6bcf	498	#define CONFIG_SYS_ATA_BASE_ADDR 0xa0000000
66fd3d1c WD	499
66fd3d1c WD	500	/* Offset for data I/O */
6d0f6bcf	501	#define CONFIG_SYS_ATA_DATA_OFFSET 0x100
66fd3d1c WD	502
66fd3d1c WD	503	/* Offset for normal register accesses */
6d0f6bcf	504	#define CONFIG_SYS_ATA_REG_OFFSET 0x100
66fd3d1c WD	505
66fd3d1c WD	506	/* Offset for alternate registers */
6d0f6bcf	507	#define CONFIG_SYS_ATA_ALT_OFFSET 0x108
66fd3d1c	508
7aa78614	509	#endif /* __CONFIG_H */