]>
Commit | Line | Data |
---|---|---|
7aa78614 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
37 | #define CONFIG_ATC 1 /* ...on a ATC board */ | |
9c4c5ae3 | 38 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
7aa78614 WD |
39 | |
40 | /* | |
41 | * select serial console configuration | |
42 | * | |
43 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
44 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
45 | * for SCC). | |
46 | * | |
47 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
48 | * defined elsewhere (for example, on the cogent platform, there are serial | |
49 | * ports on the motherboard which are used for the serial console - see | |
50 | * cogent/cma101/serial.[ch]). | |
51 | */ | |
52 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
53 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
54 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
55 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
56 | ||
57 | #define CONFIG_BAUDRATE 115200 | |
58 | ||
59 | /* | |
60 | * select ethernet configuration | |
61 | * | |
62 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
63 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
64 | * for FCC) | |
65 | * | |
66 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 67 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
7aa78614 WD |
68 | */ |
69 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
70 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
71 | #define CONFIG_ETHER_ON_FCC | |
72 | ||
73 | #define CONFIG_NET_MULTI | |
74 | #define CONFIG_ETHER_ON_FCC2 | |
75 | ||
76 | /* | |
77 | * - Rx-CLK is CLK13 | |
78 | * - Tx-CLK is CLK14 | |
79 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
80 | * - Enable Full Duplex in FSMR | |
81 | */ | |
82 | # define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) | |
83 | # define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
84 | # define CFG_CPMFCR_RAMTYPE 0 | |
85 | # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
86 | ||
87 | #define CONFIG_ETHER_ON_FCC3 | |
88 | ||
89 | /* | |
90 | * - Rx-CLK is CLK15 | |
91 | * - Tx-CLK is CLK16 | |
92 | * - RAM for BD/Buffers is on the local Bus (see 28-13) | |
93 | * - Enable Half Duplex in FSMR | |
94 | */ | |
95 | # define CFG_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) | |
96 | # define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) | |
97 | ||
98 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
99 | #define CONFIG_8260_CLKIN 64000000 /* in Hz */ | |
100 | ||
101 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
102 | ||
103 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */ | |
104 | ||
105 | #define CONFIG_PREBOOT \ | |
106 | "echo;" \ | |
32bf3d14 | 107 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\ |
7aa78614 WD |
108 | "echo" |
109 | ||
110 | #undef CONFIG_BOOTARGS | |
111 | #define CONFIG_BOOTCOMMAND \ | |
112 | "bootp;" \ | |
113 | "setenv bootargs root=/dev/nfs rw " \ | |
53677ef1 | 114 | "nfsroot=${serverip}:${rootpath} " \ |
fe126d8b | 115 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\ |
7aa78614 WD |
116 | "bootm" |
117 | ||
118 | /*----------------------------------------------------------------------- | |
119 | * Miscellaneous configuration options | |
120 | */ | |
121 | ||
122 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
123 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
124 | ||
2fd90ce5 JL |
125 | |
126 | /* | |
127 | * BOOTP options | |
128 | */ | |
129 | #define CONFIG_BOOTP_SUBNETMASK | |
130 | #define CONFIG_BOOTP_GATEWAY | |
131 | #define CONFIG_BOOTP_HOSTNAME | |
132 | #define CONFIG_BOOTP_BOOTPATH | |
133 | #define CONFIG_BOOTP_BOOTFILESIZE | |
7aa78614 | 134 | |
15ef8a5d | 135 | |
0b361c91 JL |
136 | /* |
137 | * Command line configuration. | |
138 | */ | |
139 | #include <config_cmd_default.h> | |
15ef8a5d | 140 | |
0b361c91 JL |
141 | #define CONFIG_CMD_EEPROM |
142 | #define CONFIG_CMD_PCI | |
143 | #define CONFIG_CMD_PCMCIA | |
144 | #define CONFIG_CMD_DATE | |
145 | #define CONFIG_CMD_IDE | |
7aa78614 | 146 | |
0b361c91 JL |
147 | |
148 | #define CONFIG_DOS_PARTITION | |
7aa78614 WD |
149 | |
150 | /* | |
151 | * Miscellaneous configurable options | |
152 | */ | |
153 | #define CFG_LONGHELP /* undef to save memory */ | |
154 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
0b361c91 | 155 | #if defined(CONFIG_CMD_KGDB) |
7aa78614 WD |
156 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
157 | #else | |
158 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
159 | #endif | |
160 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
161 | #define CFG_MAXARGS 16 /* max number of command args */ | |
162 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
163 | ||
164 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
165 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
166 | ||
167 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
168 | ||
66fd3d1c WD |
169 | #define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ |
170 | ||
7aa78614 WD |
171 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
172 | ||
173 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
174 | ||
175 | #define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */ | |
176 | ||
177 | #define CFG_ALLOC_DPRAM | |
178 | ||
179 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
180 | ||
181 | #define CONFIG_SPI | |
182 | ||
15ef8a5d WD |
183 | #define CONFIG_RTC_DS12887 |
184 | ||
53677ef1 WD |
185 | #define RTC_BASE_ADDR 0xF5000000 |
186 | #define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800 | |
187 | #define RTC_PORT_DATA RTC_BASE_ADDR + 0x808 | |
15ef8a5d WD |
188 | |
189 | #define CONFIG_MISC_INIT_R | |
190 | ||
7aa78614 WD |
191 | /* |
192 | * For booting Linux, the board info and command line data | |
193 | * have to be in the first 8 MB of memory, since this is | |
194 | * the maximum mapped by the Linux kernel during initialization. | |
195 | */ | |
196 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
197 | ||
198 | /*----------------------------------------------------------------------- | |
199 | * Flash configuration | |
200 | */ | |
201 | ||
7aa78614 WD |
202 | #define CFG_FLASH_BASE 0xFF000000 |
203 | #define CFG_FLASH_SIZE 0x00800000 | |
204 | ||
205 | /*----------------------------------------------------------------------- | |
206 | * FLASH organization | |
207 | */ | |
208 | #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
209 | #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
210 | ||
211 | #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ | |
212 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
213 | ||
214 | #define CONFIG_FLASH_16BIT | |
215 | ||
216 | /*----------------------------------------------------------------------- | |
217 | * Hard Reset Configuration Words | |
218 | * | |
219 | * if you change bits in the HRCW, you must also change the CFG_* | |
220 | * defines for the various registers affected by the HRCW e.g. changing | |
221 | * HRCW_DPPCxx requires you to also change CFG_SIUMCR. | |
222 | */ | |
223 | #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ | |
9a0e21a3 | 224 | HRCW_BPS10 |\ |
7aa78614 WD |
225 | HRCW_APPC10) |
226 | ||
227 | /* no slaves so just fill with zeros */ | |
228 | #define CFG_HRCW_SLAVE1 0 | |
229 | #define CFG_HRCW_SLAVE2 0 | |
230 | #define CFG_HRCW_SLAVE3 0 | |
231 | #define CFG_HRCW_SLAVE4 0 | |
232 | #define CFG_HRCW_SLAVE5 0 | |
233 | #define CFG_HRCW_SLAVE6 0 | |
234 | #define CFG_HRCW_SLAVE7 0 | |
235 | ||
236 | /*----------------------------------------------------------------------- | |
237 | * Internal Memory Mapped Register | |
238 | */ | |
239 | #define CFG_IMMR 0xF0000000 | |
240 | ||
241 | /*----------------------------------------------------------------------- | |
242 | * Definitions for initial stack pointer and data area (in DPRAM) | |
243 | */ | |
244 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
245 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
246 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ | |
247 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
248 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
249 | ||
250 | /*----------------------------------------------------------------------- | |
251 | * Start addresses for the final memory configuration | |
252 | * (Set up by the startup code) | |
253 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
254 | * | |
255 | * 60x SDRAM is mapped at CFG_SDRAM_BASE. | |
256 | */ | |
257 | #define CFG_SDRAM_BASE 0x00000000 | |
258 | #define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ | |
259 | #define CFG_MONITOR_BASE TEXT_BASE | |
e6009629 | 260 | #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
7aa78614 WD |
261 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ |
262 | ||
263 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
264 | # define CFG_RAMBOOT | |
265 | #endif | |
266 | ||
66fd3d1c WD |
267 | #define CONFIG_PCI |
268 | #define CONFIG_PCI_PNP | |
5d232d0e | 269 | #define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ |
66fd3d1c | 270 | |
7aa78614 WD |
271 | #if 1 |
272 | /* environment is in Flash */ | |
273 | #define CFG_ENV_IS_IN_FLASH 1 | |
e6009629 | 274 | # define CFG_ENV_ADDR (CFG_FLASH_BASE+0x30000) |
7aa78614 WD |
275 | # define CFG_ENV_SIZE 0x10000 |
276 | # define CFG_ENV_SECT_SIZE 0x10000 | |
277 | #else | |
bb1f8b4f | 278 | #define CONFIG_ENV_IS_IN_EEPROM 1 |
7aa78614 WD |
279 | #define CFG_ENV_OFFSET 0 |
280 | #define CFG_ENV_SIZE 2048 | |
281 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ | |
282 | #endif | |
283 | /* | |
284 | * Internal Definitions | |
285 | * | |
286 | * Boot Flags | |
287 | */ | |
288 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ | |
289 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
290 | ||
291 | ||
292 | /*----------------------------------------------------------------------- | |
293 | * Cache Configuration | |
294 | */ | |
295 | #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ | |
0b361c91 | 296 | #if defined(CONFIG_CMD_KGDB) |
7aa78614 WD |
297 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
298 | #endif | |
299 | ||
300 | /*----------------------------------------------------------------------- | |
301 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
302 | *----------------------------------------------------------------------- | |
303 | * HID0 also contains cache control - initially enable both caches and | |
304 | * invalidate contents, then the final state leaves only the instruction | |
305 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
306 | * but Soft reset does not. | |
307 | * | |
308 | * HID1 has only read-only information - nothing to set. | |
309 | */ | |
310 | #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ | |
8bde7f77 | 311 | HID0_DCI|HID0_IFEM|HID0_ABE) |
7aa78614 WD |
312 | #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) |
313 | #define CFG_HID2 0 | |
314 | ||
315 | /*----------------------------------------------------------------------- | |
316 | * RMR - Reset Mode Register 5-5 | |
317 | *----------------------------------------------------------------------- | |
318 | * turn on Checkstop Reset Enable | |
319 | */ | |
320 | #define CFG_RMR RMR_CSRE | |
321 | ||
322 | /*----------------------------------------------------------------------- | |
323 | * BCR - Bus Configuration 4-25 | |
324 | *----------------------------------------------------------------------- | |
325 | */ | |
326 | #define BCR_APD01 0x10000000 | |
327 | #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ | |
328 | ||
329 | /*----------------------------------------------------------------------- | |
330 | * SIUMCR - SIU Module Configuration 4-31 | |
331 | *----------------------------------------------------------------------- | |
332 | */ | |
9a0e21a3 | 333 | #define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_APPC10|\ |
7aa78614 WD |
334 | SIUMCR_CS10PC00|SIUMCR_BCTLC10) |
335 | ||
336 | /*----------------------------------------------------------------------- | |
337 | * SYPCR - System Protection Control 4-35 | |
338 | * SYPCR can only be written once after reset! | |
339 | *----------------------------------------------------------------------- | |
340 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
341 | */ | |
342 | #if defined(CONFIG_WATCHDOG) | |
343 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
8bde7f77 | 344 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
7aa78614 WD |
345 | #else |
346 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
8bde7f77 | 347 | SYPCR_SWRI|SYPCR_SWP) |
7aa78614 WD |
348 | #endif /* CONFIG_WATCHDOG */ |
349 | ||
350 | /*----------------------------------------------------------------------- | |
351 | * TMCNTSC - Time Counter Status and Control 4-40 | |
352 | *----------------------------------------------------------------------- | |
353 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
354 | * and enable Time Counter | |
355 | */ | |
356 | #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) | |
357 | ||
358 | /*----------------------------------------------------------------------- | |
359 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
360 | *----------------------------------------------------------------------- | |
361 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
362 | * Periodic timer | |
363 | */ | |
364 | #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) | |
365 | ||
366 | /*----------------------------------------------------------------------- | |
367 | * SCCR - System Clock Control 9-8 | |
368 | *----------------------------------------------------------------------- | |
369 | * Ensure DFBRG is Divide by 16 | |
370 | */ | |
371 | #define CFG_SCCR SCCR_DFBRG01 | |
372 | ||
373 | /*----------------------------------------------------------------------- | |
374 | * RCCR - RISC Controller Configuration 13-7 | |
375 | *----------------------------------------------------------------------- | |
376 | */ | |
377 | #define CFG_RCCR 0 | |
378 | ||
379 | #define CFG_MIN_AM_MASK 0xC0000000 | |
380 | /*----------------------------------------------------------------------- | |
381 | * MPTPR - Memory Refresh Timer Prescaler Register 10-18 | |
382 | *----------------------------------------------------------------------- | |
383 | */ | |
384 | #define CFG_MPTPR 0x1F00 | |
385 | ||
386 | /*----------------------------------------------------------------------- | |
387 | * PSRT - Refresh Timer Register 10-16 | |
388 | *----------------------------------------------------------------------- | |
389 | */ | |
390 | #define CFG_PSRT 0x0f | |
391 | ||
392 | /*----------------------------------------------------------------------- | |
393 | * PSRT - SDRAM Mode Register 10-10 | |
394 | *----------------------------------------------------------------------- | |
395 | */ | |
396 | ||
397 | /* SDRAM initialization values for 8-column chips | |
398 | */ | |
399 | #define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ | |
400 | ORxS_BPD_4 |\ | |
f7de16ae WD |
401 | ORxS_ROWST_PBI1_A7 |\ |
402 | ORxS_NUMR_12) | |
7aa78614 | 403 | |
f7de16ae WD |
404 | #define CFG_PSDMR_8COL (PSDMR_PBI |\ |
405 | PSDMR_SDAM_A15_IS_A5 |\ | |
406 | PSDMR_BSMA_A15_A17 |\ | |
407 | PSDMR_SDA10_PBI1_A7 |\ | |
7aa78614 | 408 | PSDMR_RFRC_7_CLK |\ |
f7de16ae WD |
409 | PSDMR_PRETOACT_3W |\ |
410 | PSDMR_ACTTORW_2W |\ | |
7aa78614 WD |
411 | PSDMR_LDOTOPRE_1C |\ |
412 | PSDMR_WRC_1C |\ | |
413 | PSDMR_CL_2) | |
414 | ||
415 | /* SDRAM initialization values for 9-column chips | |
416 | */ | |
417 | #define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ | |
418 | ORxS_BPD_4 |\ | |
f7de16ae WD |
419 | ORxS_ROWST_PBI1_A6 |\ |
420 | ORxS_NUMR_12) | |
7aa78614 | 421 | |
f7de16ae WD |
422 | #define CFG_PSDMR_9COL (PSDMR_PBI |\ |
423 | PSDMR_SDAM_A16_IS_A5 |\ | |
424 | PSDMR_BSMA_A15_A17 |\ | |
425 | PSDMR_SDA10_PBI1_A6 |\ | |
7aa78614 | 426 | PSDMR_RFRC_7_CLK |\ |
f7de16ae WD |
427 | PSDMR_PRETOACT_3W |\ |
428 | PSDMR_ACTTORW_2W |\ | |
7aa78614 WD |
429 | PSDMR_LDOTOPRE_1C |\ |
430 | PSDMR_WRC_1C |\ | |
431 | PSDMR_CL_2) | |
432 | ||
433 | /* | |
434 | * Init Memory Controller: | |
435 | * | |
436 | * Bank Bus Machine PortSz Device | |
437 | * ---- --- ------- ------ ------ | |
438 | * 0 60x GPCM 8 bit Boot ROM | |
439 | * 1 60x GPCM 64 bit FLASH | |
440 | * 2 60x SDRAM 64 bit SDRAM | |
441 | * | |
442 | */ | |
443 | ||
444 | #define CFG_MRS_OFFS 0x00000000 | |
445 | ||
446 | /* Bank 0 - FLASH | |
447 | */ | |
448 | #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ | |
8bde7f77 WD |
449 | BRx_PS_16 |\ |
450 | BRx_MS_GPCM_P |\ | |
451 | BRx_V) | |
7aa78614 WD |
452 | |
453 | #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ | |
8bde7f77 WD |
454 | ORxG_CSNT |\ |
455 | ORxG_ACS_DIV1 |\ | |
456 | ORxG_SCY_3_CLK |\ | |
457 | ORxU_EHTR_8IDLE) | |
7aa78614 WD |
458 | |
459 | ||
460 | /* Bank 2 - 60x bus SDRAM | |
461 | */ | |
462 | #ifndef CFG_RAMBOOT | |
463 | #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ | |
8bde7f77 WD |
464 | BRx_PS_64 |\ |
465 | BRx_MS_SDRAM_P |\ | |
466 | BRx_V) | |
7aa78614 WD |
467 | |
468 | #define CFG_OR2_PRELIM CFG_OR2_8COL | |
469 | ||
470 | #define CFG_PSDMR CFG_PSDMR_8COL | |
471 | #endif /* CFG_RAMBOOT */ | |
472 | ||
15ef8a5d | 473 | #define CFG_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\ |
8bde7f77 WD |
474 | BRx_PS_8 |\ |
475 | BRx_MS_UPMA |\ | |
476 | BRx_V) | |
15ef8a5d WD |
477 | |
478 | #define CFG_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI) | |
8bde7f77 | 479 | |
66fd3d1c WD |
480 | /*----------------------------------------------------------------------- |
481 | * PCMCIA stuff | |
482 | *----------------------------------------------------------------------- | |
483 | * | |
484 | */ | |
485 | #define CONFIG_I82365 | |
486 | ||
487 | #define CFG_PCMCIA_MEM_ADDR 0x81000000 | |
488 | #define CFG_PCMCIA_MEM_SIZE 0x1000 | |
489 | ||
490 | /*----------------------------------------------------------------------- | |
491 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
492 | *----------------------------------------------------------------------- | |
493 | */ | |
494 | ||
495 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
496 | ||
497 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
498 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
499 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
500 | ||
501 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
502 | #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
503 | ||
504 | #define CFG_ATA_IDE0_OFFSET 0x0000 | |
505 | ||
506 | #define CFG_ATA_BASE_ADDR 0xa0000000 | |
507 | ||
508 | /* Offset for data I/O */ | |
509 | #define CFG_ATA_DATA_OFFSET 0x100 | |
510 | ||
511 | /* Offset for normal register accesses */ | |
512 | #define CFG_ATA_REG_OFFSET 0x100 | |
513 | ||
514 | /* Offset for alternate registers */ | |
515 | #define CFG_ATA_ALT_OFFSET 0x108 | |
516 | ||
7aa78614 | 517 | #endif /* __CONFIG_H */ |