projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 7aa78614 WD |
1 | /* |
| 2 | * (C) Copyright 2001 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | #ifndef __CONFIG_H | |
| 29 | #define __CONFIG_H | |
| 30 | ||
| 31 | /* | |
| 32 | * High Level Configuration Options | |
| 33 | * (easy to change) | |
| 34 | */ | |
| 35 | ||
| 36 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
| 37 | #define CONFIG_ATC 1 /* ...on a ATC board */ | |
| 38 | ||
| 39 | /* | |
| 40 | * select serial console configuration | |
| 41 | * | |
| 42 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
| 43 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
| 44 | * for SCC). | |
| 45 | * | |
| 46 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
| 47 | * defined elsewhere (for example, on the cogent platform, there are serial | |
| 48 | * ports on the motherboard which are used for the serial console - see | |
| 49 | * cogent/cma101/serial.[ch]). | |
| 50 | */ | |
| 51 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
| 52 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
| 53 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
| 54 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
| 55 | ||
| 56 | #define CONFIG_BAUDRATE 115200 | |
| 57 | ||
| 58 | /* | |
| 59 | * select ethernet configuration | |
| 60 | * | |
| 61 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
| 62 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
| 63 | * for FCC) | |
| 64 | * | |
| 65 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
| 66 | * defined elsewhere (as for the console), or CFG_CMD_NET must be removed | |
| 67 | * from CONFIG_COMMANDS to remove support for networking. | |
| 68 | * | |
| 69 | */ | |
| 70 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
| 71 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
| 72 | #define CONFIG_ETHER_ON_FCC | |
| 73 | ||
| 74 | #define CONFIG_NET_MULTI | |
| 75 | #define CONFIG_ETHER_ON_FCC2 | |
| 76 | ||
| 77 | /* | |
| 78 | * - Rx-CLK is CLK13 | |
| 79 | * - Tx-CLK is CLK14 | |
| 80 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
| 81 | * - Enable Full Duplex in FSMR | |
| 82 | */ | |
| 83 | # define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) | |
| 84 | # define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
| 85 | # define CFG_CPMFCR_RAMTYPE 0 | |
| 86 | # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
| 87 | ||
| 88 | #define CONFIG_ETHER_ON_FCC3 | |
| 89 | ||
| 90 | /* | |
| 91 | * - Rx-CLK is CLK15 | |
| 92 | * - Tx-CLK is CLK16 | |
| 93 | * - RAM for BD/Buffers is on the local Bus (see 28-13) | |
| 94 | * - Enable Half Duplex in FSMR | |
| 95 | */ | |
| 96 | # define CFG_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) | |
| 97 | # define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) | |
| 98 | ||
| 99 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
| 100 | #define CONFIG_8260_CLKIN 64000000 /* in Hz */ | |
| 101 | ||
| 102 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 103 | ||
| 104 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */ | |
| 105 | ||
| 106 | #define CONFIG_PREBOOT \ | |
| 107 | "echo;" \ | |
| 108 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\ | |
| 109 | "echo" | |
| 110 | ||
| 111 | #undef CONFIG_BOOTARGS | |
| 112 | #define CONFIG_BOOTCOMMAND \ | |
| 113 | "bootp;" \ | |
| 114 | "setenv bootargs root=/dev/nfs rw " \ | |
| 115 | "nfsroot=$(serverip):$(rootpath) " \ | |
| 116 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\ | |
| 117 | "bootm" | |
| 118 | ||
| 119 | /*----------------------------------------------------------------------- | |
| 120 | * Miscellaneous configuration options | |
| 121 | */ | |
| 122 | ||
| 123 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 124 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
| 125 | ||
| 126 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) | |
| 127 | ||
| 128 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_EEPROM) | |
| 129 | ||
| 130 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
| 131 | #include <cmd_confdefs.h> | |
| 132 | ||
| 133 | /* | |
| 134 | * Miscellaneous configurable options | |
| 135 | */ | |
| 136 | #define CFG_LONGHELP /* undef to save memory */ | |
| 137 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 138 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 139 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 140 | #else | |
| 141 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 142 | #endif | |
| 143 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 144 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 145 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 146 | ||
| 147 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
| 148 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
| 149 | ||
| 150 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
| 151 | ||
| 152 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
| 153 | ||
| 154 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
| 155 | ||
| 156 | #define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */ | |
| 157 | ||
| 158 | #define CFG_ALLOC_DPRAM | |
| 159 | ||
| 160 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 161 | ||
| 162 | #define CONFIG_SPI | |
| 163 | ||
| 164 | /* | |
| 165 | * For booting Linux, the board info and command line data | |
| 166 | * have to be in the first 8 MB of memory, since this is | |
| 167 | * the maximum mapped by the Linux kernel during initialization. | |
| 168 | */ | |
| 169 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 170 | ||
| 171 | /*----------------------------------------------------------------------- | |
| 172 | * Flash configuration | |
| 173 | */ | |
| 174 | ||
| 175 | #define CFG_BOOTROM_BASE 0xFF800000 | |
| 176 | #define CFG_BOOTROM_SIZE 0x00080000 | |
| 177 | #define CFG_FLASH_BASE 0xFF000000 | |
| 178 | #define CFG_FLASH_SIZE 0x00800000 | |
| 179 | ||
| 180 | /*----------------------------------------------------------------------- | |
| 181 | * FLASH organization | |
| 182 | */ | |
| 183 | #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
| 184 | #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
| 185 | ||
| 186 | #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ | |
| 187 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
| 188 | ||
| 189 | #define CONFIG_FLASH_16BIT | |
| 190 | ||
| 191 | /*----------------------------------------------------------------------- | |
| 192 | * Hard Reset Configuration Words | |
| 193 | * | |
| 194 | * if you change bits in the HRCW, you must also change the CFG_* | |
| 195 | * defines for the various registers affected by the HRCW e.g. changing | |
| 196 | * HRCW_DPPCxx requires you to also change CFG_SIUMCR. | |
| 197 | */ | |
| 198 | #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ | |
| 199 | HRCW_BPS10 | HRCW_DPPC10 |\ | |
| 200 | HRCW_APPC10) | |
| 201 | ||
| 202 | /* no slaves so just fill with zeros */ | |
| 203 | #define CFG_HRCW_SLAVE1 0 | |
| 204 | #define CFG_HRCW_SLAVE2 0 | |
| 205 | #define CFG_HRCW_SLAVE3 0 | |
| 206 | #define CFG_HRCW_SLAVE4 0 | |
| 207 | #define CFG_HRCW_SLAVE5 0 | |
| 208 | #define CFG_HRCW_SLAVE6 0 | |
| 209 | #define CFG_HRCW_SLAVE7 0 | |
| 210 | ||
| 211 | /*----------------------------------------------------------------------- | |
| 212 | * Internal Memory Mapped Register | |
| 213 | */ | |
| 214 | #define CFG_IMMR 0xF0000000 | |
| 215 | ||
| 216 | /*----------------------------------------------------------------------- | |
| 217 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 218 | */ | |
| 219 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
| 220 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
| 221 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ | |
| 222 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 223 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 224 | ||
| 225 | /*----------------------------------------------------------------------- | |
| 226 | * Start addresses for the final memory configuration | |
| 227 | * (Set up by the startup code) | |
| 228 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
| 229 | * | |
| 230 | * 60x SDRAM is mapped at CFG_SDRAM_BASE. | |
| 231 | */ | |
| 232 | #define CFG_SDRAM_BASE 0x00000000 | |
| 233 | #define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ | |
| 234 | #define CFG_MONITOR_BASE TEXT_BASE | |
| e6009629 | 235 | #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
| 7aa78614 WD |
236 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ |
| 237 | ||
| 238 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
| 239 | # define CFG_RAMBOOT | |
| 240 | #endif | |
| 241 | ||
| 242 | #if 1 | |
| 243 | /* environment is in Flash */ | |
| 244 | #define CFG_ENV_IS_IN_FLASH 1 | |
| e6009629 | 245 | # define CFG_ENV_ADDR (CFG_FLASH_BASE+0x30000) |
| 7aa78614 WD |
246 | # define CFG_ENV_SIZE 0x10000 |
| 247 | # define CFG_ENV_SECT_SIZE 0x10000 | |
| 248 | #else | |
| 249 | #define CFG_ENV_IS_IN_EEPROM 1 | |
| 250 | #define CFG_ENV_OFFSET 0 | |
| 251 | #define CFG_ENV_SIZE 2048 | |
| 252 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ | |
| 253 | #endif | |
| 254 | /* | |
| 255 | * Internal Definitions | |
| 256 | * | |
| 257 | * Boot Flags | |
| 258 | */ | |
| 259 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ | |
| 260 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 261 | ||
| 262 | ||
| 263 | /*----------------------------------------------------------------------- | |
| 264 | * Cache Configuration | |
| 265 | */ | |
| 266 | #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ | |
| 267 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 268 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
| 269 | #endif | |
| 270 | ||
| 271 | /*----------------------------------------------------------------------- | |
| 272 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
| 273 | *----------------------------------------------------------------------- | |
| 274 | * HID0 also contains cache control - initially enable both caches and | |
| 275 | * invalidate contents, then the final state leaves only the instruction | |
| 276 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
| 277 | * but Soft reset does not. | |
| 278 | * | |
| 279 | * HID1 has only read-only information - nothing to set. | |
| 280 | */ | |
| 281 | #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ | |
| 282 | HID0_DCI|HID0_IFEM|HID0_ABE) | |
| 283 | #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) | |
| 284 | #define CFG_HID2 0 | |
| 285 | ||
| 286 | /*----------------------------------------------------------------------- | |
| 287 | * RMR - Reset Mode Register 5-5 | |
| 288 | *----------------------------------------------------------------------- | |
| 289 | * turn on Checkstop Reset Enable | |
| 290 | */ | |
| 291 | #define CFG_RMR RMR_CSRE | |
| 292 | ||
| 293 | /*----------------------------------------------------------------------- | |
| 294 | * BCR - Bus Configuration 4-25 | |
| 295 | *----------------------------------------------------------------------- | |
| 296 | */ | |
| 297 | #define BCR_APD01 0x10000000 | |
| 298 | #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ | |
| 299 | ||
| 300 | /*----------------------------------------------------------------------- | |
| 301 | * SIUMCR - SIU Module Configuration 4-31 | |
| 302 | *----------------------------------------------------------------------- | |
| 303 | */ | |
| 304 | #define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC10|SIUMCR_APPC10|\ | |
| 305 | SIUMCR_CS10PC00|SIUMCR_BCTLC10) | |
| 306 | ||
| 307 | /*----------------------------------------------------------------------- | |
| 308 | * SYPCR - System Protection Control 4-35 | |
| 309 | * SYPCR can only be written once after reset! | |
| 310 | *----------------------------------------------------------------------- | |
| 311 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
| 312 | */ | |
| 313 | #if defined(CONFIG_WATCHDOG) | |
| 314 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
| 315 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) | |
| 316 | #else | |
| 317 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
| 318 | SYPCR_SWRI|SYPCR_SWP) | |
| 319 | #endif /* CONFIG_WATCHDOG */ | |
| 320 | ||
| 321 | /*----------------------------------------------------------------------- | |
| 322 | * TMCNTSC - Time Counter Status and Control 4-40 | |
| 323 | *----------------------------------------------------------------------- | |
| 324 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
| 325 | * and enable Time Counter | |
| 326 | */ | |
| 327 | #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) | |
| 328 | ||
| 329 | /*----------------------------------------------------------------------- | |
| 330 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
| 331 | *----------------------------------------------------------------------- | |
| 332 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
| 333 | * Periodic timer | |
| 334 | */ | |
| 335 | #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) | |
| 336 | ||
| 337 | /*----------------------------------------------------------------------- | |
| 338 | * SCCR - System Clock Control 9-8 | |
| 339 | *----------------------------------------------------------------------- | |
| 340 | * Ensure DFBRG is Divide by 16 | |
| 341 | */ | |
| 342 | #define CFG_SCCR SCCR_DFBRG01 | |
| 343 | ||
| 344 | /*----------------------------------------------------------------------- | |
| 345 | * RCCR - RISC Controller Configuration 13-7 | |
| 346 | *----------------------------------------------------------------------- | |
| 347 | */ | |
| 348 | #define CFG_RCCR 0 | |
| 349 | ||
| 350 | #define CFG_MIN_AM_MASK 0xC0000000 | |
| 351 | /*----------------------------------------------------------------------- | |
| 352 | * MPTPR - Memory Refresh Timer Prescaler Register 10-18 | |
| 353 | *----------------------------------------------------------------------- | |
| 354 | */ | |
| 355 | #define CFG_MPTPR 0x1F00 | |
| 356 | ||
| 357 | /*----------------------------------------------------------------------- | |
| 358 | * PSRT - Refresh Timer Register 10-16 | |
| 359 | *----------------------------------------------------------------------- | |
| 360 | */ | |
| 361 | #define CFG_PSRT 0x0f | |
| 362 | ||
| 363 | /*----------------------------------------------------------------------- | |
| 364 | * PSRT - SDRAM Mode Register 10-10 | |
| 365 | *----------------------------------------------------------------------- | |
| 366 | */ | |
| 367 | ||
| 368 | /* SDRAM initialization values for 8-column chips | |
| 369 | */ | |
| 370 | #define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ | |
| 371 | ORxS_BPD_4 |\ | |
| f7de16ae WD |
372 | ORxS_ROWST_PBI1_A7 |\ |
| 373 | ORxS_NUMR_12) | |
| 7aa78614 | 374 | |
| f7de16ae WD |
375 | #define CFG_PSDMR_8COL (PSDMR_PBI |\ |
| 376 | PSDMR_SDAM_A15_IS_A5 |\ | |
| 377 | PSDMR_BSMA_A15_A17 |\ | |
| 378 | PSDMR_SDA10_PBI1_A7 |\ | |
| 7aa78614 | 379 | PSDMR_RFRC_7_CLK |\ |
| f7de16ae WD |
380 | PSDMR_PRETOACT_3W |\ |
| 381 | PSDMR_ACTTORW_2W |\ | |
| 7aa78614 WD |
382 | PSDMR_LDOTOPRE_1C |\ |
| 383 | PSDMR_WRC_1C |\ | |
| 384 | PSDMR_CL_2) | |
| 385 | ||
| 386 | /* SDRAM initialization values for 9-column chips | |
| 387 | */ | |
| 388 | #define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ | |
| 389 | ORxS_BPD_4 |\ | |
| f7de16ae WD |
390 | ORxS_ROWST_PBI1_A6 |\ |
| 391 | ORxS_NUMR_12) | |
| 7aa78614 | 392 | |
| f7de16ae WD |
393 | #define CFG_PSDMR_9COL (PSDMR_PBI |\ |
| 394 | PSDMR_SDAM_A16_IS_A5 |\ | |
| 395 | PSDMR_BSMA_A15_A17 |\ | |
| 396 | PSDMR_SDA10_PBI1_A6 |\ | |
| 7aa78614 | 397 | PSDMR_RFRC_7_CLK |\ |
| f7de16ae WD |
398 | PSDMR_PRETOACT_3W |\ |
| 399 | PSDMR_ACTTORW_2W |\ | |
| 7aa78614 WD |
400 | PSDMR_LDOTOPRE_1C |\ |
| 401 | PSDMR_WRC_1C |\ | |
| 402 | PSDMR_CL_2) | |
| 403 | ||
| 404 | /* | |
| 405 | * Init Memory Controller: | |
| 406 | * | |
| 407 | * Bank Bus Machine PortSz Device | |
| 408 | * ---- --- ------- ------ ------ | |
| 409 | * 0 60x GPCM 8 bit Boot ROM | |
| 410 | * 1 60x GPCM 64 bit FLASH | |
| 411 | * 2 60x SDRAM 64 bit SDRAM | |
| 412 | * | |
| 413 | */ | |
| 414 | ||
| 415 | #define CFG_MRS_OFFS 0x00000000 | |
| 416 | ||
| 417 | /* Bank 0 - FLASH | |
| 418 | */ | |
| 419 | #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ | |
| 420 | BRx_PS_16 |\ | |
| 421 | BRx_MS_GPCM_P |\ | |
| 422 | BRx_V) | |
| 423 | ||
| 424 | #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ | |
| 425 | ORxG_CSNT |\ | |
| 426 | ORxG_ACS_DIV1 |\ | |
| 427 | ORxG_SCY_3_CLK |\ | |
| 428 | ORxU_EHTR_8IDLE) | |
| 429 | ||
| 430 | ||
| 431 | /* Bank 2 - 60x bus SDRAM | |
| 432 | */ | |
| 433 | #ifndef CFG_RAMBOOT | |
| 434 | #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ | |
| 435 | BRx_PS_64 |\ | |
| 436 | BRx_MS_SDRAM_P |\ | |
| 437 | BRx_V) | |
| 438 | ||
| 439 | #define CFG_OR2_PRELIM CFG_OR2_8COL | |
| 440 | ||
| 441 | #define CFG_PSDMR CFG_PSDMR_8COL | |
| 442 | #endif /* CFG_RAMBOOT */ | |
| 443 | ||
| 444 | #endif /* __CONFIG_H */ |