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Commit | Line | Data |
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6b443944 HS |
1 | /* |
2 | * Copyright (C) 2006 Atmel Corporation | |
3 | * | |
4 | * Configuration settings for the AVR32 Network Gateway | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
6b443944 HS |
7 | */ |
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
5d73bc7a | 11 | #include <asm/arch/hardware.h> |
a23e277c | 12 | |
b78431a4 AB |
13 | #define CONFIG_AT32AP |
14 | #define CONFIG_AT32AP7000 | |
15 | #define CONFIG_ATNGW100 | |
6b443944 | 16 | |
fb1e3eb9 AB |
17 | #define CONFIG_BOARD_EARLY_INIT_R |
18 | ||
6b443944 HS |
19 | /* |
20 | * Set up the PLL to run at 140 MHz, the CPU to run at the PLL | |
21 | * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency | |
22 | * and the PBA bus to run at 1/4 the PLL frequency. | |
23 | */ | |
b78431a4 AB |
24 | #define CONFIG_PLL |
25 | #define CONFIG_SYS_POWER_MANAGER | |
6d0f6bcf JCPV |
26 | #define CONFIG_SYS_OSC0_HZ 20000000 |
27 | #define CONFIG_SYS_PLL0_DIV 1 | |
28 | #define CONFIG_SYS_PLL0_MUL 7 | |
29 | #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 | |
30 | #define CONFIG_SYS_CLKDIV_CPU 0 | |
31 | #define CONFIG_SYS_CLKDIV_HSB 1 | |
32 | #define CONFIG_SYS_CLKDIV_PBA 2 | |
33 | #define CONFIG_SYS_CLKDIV_PBB 1 | |
6b443944 | 34 | |
1f36f73f HS |
35 | /* Reserve VM regions for SDRAM and NOR flash */ |
36 | #define CONFIG_SYS_NR_VM_REGIONS 2 | |
37 | ||
6b443944 HS |
38 | /* |
39 | * The PLLOPT register controls the PLL like this: | |
40 | * icp = PLLOPT<2> | |
41 | * ivco = PLLOPT<1:0> | |
42 | * | |
43 | * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). | |
44 | */ | |
6d0f6bcf | 45 | #define CONFIG_SYS_PLL0_OPT 0x04 |
6b443944 | 46 | |
f4278b71 AB |
47 | #define CONFIG_USART_BASE ATMEL_BASE_USART1 |
48 | #define CONFIG_USART_ID 1 | |
6b443944 | 49 | /* User serviceable stuff */ |
6b443944 | 50 | |
b78431a4 AB |
51 | #define CONFIG_CMDLINE_TAG |
52 | #define CONFIG_SETUP_MEMORY_TAGS | |
53 | #define CONFIG_INITRD_TAG | |
6b443944 | 54 | |
6b443944 HS |
55 | #define CONFIG_BOOTARGS \ |
56 | "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2" | |
57 | #define CONFIG_BOOTCOMMAND \ | |
58 | "fsload; bootm" | |
59 | ||
6b443944 HS |
60 | |
61 | /* | |
62 | * After booting the board for the first time, new ethernet addresses | |
63 | * should be generated and assigned to the environment variables | |
64 | * "ethaddr" and "eth1addr". This is normally done during production. | |
65 | */ | |
b78431a4 | 66 | #define CONFIG_OVERWRITE_ETHADDR_ONCE |
6b443944 HS |
67 | |
68 | /* | |
69 | * BOOTP/DHCP options | |
70 | */ | |
71 | #define CONFIG_BOOTP_SUBNETMASK | |
72 | #define CONFIG_BOOTP_GATEWAY | |
73 | ||
6b443944 HS |
74 | /* |
75 | * Command line configuration. | |
76 | */ | |
55ac7a74 | 77 | |
b78431a4 AB |
78 | #define CONFIG_ATMEL_USART |
79 | #define CONFIG_MACB | |
80 | #define CONFIG_PORTMUX_PIO | |
6d0f6bcf | 81 | #define CONFIG_SYS_NR_PIOS 5 |
b78431a4 | 82 | #define CONFIG_SYS_HSDRAMC |
72fa4679 | 83 | #define CONFIG_GENERIC_ATMEL_MCI |
b78431a4 | 84 | #define CONFIG_ATMEL_SPI |
5f723a3b | 85 | |
6d0f6bcf JCPV |
86 | #define CONFIG_SYS_DCACHE_LINESZ 32 |
87 | #define CONFIG_SYS_ICACHE_LINESZ 32 | |
6b443944 HS |
88 | |
89 | #define CONFIG_NR_DRAM_BANKS 1 | |
90 | ||
b78431a4 AB |
91 | #define CONFIG_SYS_FLASH_CFI |
92 | #define CONFIG_FLASH_CFI_DRIVER | |
6b443944 | 93 | |
6d0f6bcf JCPV |
94 | #define CONFIG_SYS_FLASH_BASE 0x00000000 |
95 | #define CONFIG_SYS_FLASH_SIZE 0x800000 | |
96 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
97 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
6b443944 | 98 | |
6d0f6bcf | 99 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
da484372 | 100 | #define CONFIG_SYS_TEXT_BASE 0x00000000 |
6b443944 | 101 | |
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE |
103 | #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE | |
104 | #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE | |
6b443944 | 105 | |
b78431a4 | 106 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 107 | #define CONFIG_ENV_SIZE 65536 |
6d0f6bcf | 108 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) |
6b443944 | 109 | |
6d0f6bcf | 110 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) |
6b443944 | 111 | |
6d0f6bcf | 112 | #define CONFIG_SYS_MALLOC_LEN (256*1024) |
6b443944 HS |
113 | |
114 | /* Allow 4MB for the kernel run-time image */ | |
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) |
116 | #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) | |
6b443944 HS |
117 | |
118 | /* Other configuration settings that shouldn't have to change all that often */ | |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_CBSIZE 256 |
120 | #define CONFIG_SYS_MAXARGS 16 | |
121 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
b78431a4 | 122 | #define CONFIG_SYS_LONGHELP |
6b443944 | 123 | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE |
125 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000) | |
2bcacc2d | 126 | |
6d0f6bcf | 127 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } |
6b443944 HS |
128 | |
129 | #endif /* __CONFIG_H */ |