[thirdparty/u-boot.git] / include / configs / atngw100mkii.h

/*
 * Copyright (C) 2006 Atmel Corporation
 *
 * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
 *
 * Configuration settings for the AVR32 Network Gateway
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/hardware.h>

#define CONFIG_AVR32
#define CONFIG_AT32AP
#define CONFIG_AT32AP7000
#define CONFIG_ATNGW100MKII

/*
 * Timer clock frequency. We're using the CPU-internal COUNT register
 * for this, so this is equivalent to the CPU core clock frequency
 */
#define CONFIG_SYS_HZ			1000

/*
 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
 * and the PBA bus to run at 1/4 the PLL frequency.
 */
#define CONFIG_PLL
#define CONFIG_SYS_POWER_MANAGER
#define CONFIG_SYS_OSC0_HZ		20000000
#define CONFIG_SYS_PLL0_DIV		1
#define CONFIG_SYS_PLL0_MUL		7
#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
/*
 * Set the CPU running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
 */
#define CONFIG_SYS_CLKDIV_CPU		0
/*
 * Set the HSB running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
 */
#define CONFIG_SYS_CLKDIV_HSB		1
/*
 * Set the PBA running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
 */
#define CONFIG_SYS_CLKDIV_PBA		2
/*
 * Set the PBB running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
 */
#define CONFIG_SYS_CLKDIV_PBB		1

/* Reserve VM regions for NOR flash, NAND flash and SDRAM */
#define CONFIG_SYS_NR_VM_REGIONS	3

/*
 * The PLLOPT register controls the PLL like this:
 *   icp = PLLOPT<2>
 *   ivco = PLLOPT<1:0>
 *
 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
 */
#define CONFIG_SYS_PLL0_OPT		0x04

#define CONFIG_USART_BASE		ATMEL_BASE_USART1
#define CONFIG_USART_ID			1

/* User serviceable stuff */
#define CONFIG_DOS_PARTITION

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

#define CONFIG_STACKSIZE		(2048)

#define CONFIG_BAUDRATE			115200
#define CONFIG_BOOTARGS							\
	"root=mtd:main rootfstype=jffs2"
#define CONFIG_BOOTCOMMAND						\
	"fsload 0x10400000 /uImage; bootm"

/*
 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
 * data on the serial line may interrupt the boot sequence.
 */
#define CONFIG_BOOTDELAY		1
#define CONFIG_AUTOBOOT
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT		\
	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR	"d"
#define CONFIG_AUTOBOOT_STOP_STR	" "

/*
 * After booting the board for the first time, new ethernet addresses
 * should be generated and assigned to the environment variables
 * "ethaddr" and "eth1addr". This is normally done during production.
 */
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_NET_MULTI

/*
 * BOOTP/DHCP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_MII

#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG

#define CONFIG_ATMEL_USART
#define CONFIG_MACB
#define CONFIG_PORTMUX_PIO
#define CONFIG_SYS_NR_PIOS		5
#define CONFIG_SYS_HSDRAMC
#define CONFIG_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_GENERIC_MMC
#define CONFIG_ATMEL_SPI

#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL

#define CONFIG_SYS_DCACHE_LINESZ	32
#define CONFIG_SYS_ICACHE_LINESZ	32

#define CONFIG_NR_DRAM_BANKS		1

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_PROTECTION

#define CONFIG_SYS_FLASH_BASE		0x00000000
#define CONFIG_SYS_FLASH_SIZE		0x800000
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	135

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_INTRAM_BASE		INTERNAL_SRAM_BASE
#define CONFIG_SYS_INTRAM_SIZE		INTERNAL_SRAM_SIZE
#define CONFIG_SYS_SDRAM_BASE		EBI_SDRAM_BASE

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE			65536
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)

#define CONFIG_SYS_MALLOC_LEN		(256*1024)
#define CONFIG_SYS_DMA_ALLOC_LEN	(16384)

/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR		(EBI_SDRAM_BASE + 0x00400000)
#define CONFIG_SYS_BOOTPARAMS_LEN	(16 * 1024)

/* Other configuration settings that shouldn't have to change all that often */
#define CONFIG_SYS_PROMPT		"U-Boot> "
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x1f00000)

#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS

#endif /* __CONFIG_H */
Commit	Line	Data
a420dfe2 AB	1	/*
	2	* Copyright (C) 2006 Atmel Corporation
	3	*
	4	* Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
	5	*
	6	* Configuration settings for the AVR32 Network Gateway
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
a420dfe2 AB	9	*/
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	#include <asm/arch/hardware.h>
	14
	15	#define CONFIG_AVR32
	16	#define CONFIG_AT32AP
	17	#define CONFIG_AT32AP7000
	18	#define CONFIG_ATNGW100MKII
	19
	20	/*
	21	* Timer clock frequency. We're using the CPU-internal COUNT register
	22	* for this, so this is equivalent to the CPU core clock frequency
	23	*/
	24	#define CONFIG_SYS_HZ 1000
	25
	26	/*
	27	* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
	28	* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
	29	* and the PBA bus to run at 1/4 the PLL frequency.
	30	*/
	31	#define CONFIG_PLL
	32	#define CONFIG_SYS_POWER_MANAGER
	33	#define CONFIG_SYS_OSC0_HZ 20000000
	34	#define CONFIG_SYS_PLL0_DIV 1
	35	#define CONFIG_SYS_PLL0_MUL 7
	36	#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
	37	/*
	38	* Set the CPU running at:
	39	* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
	40	*/
	41	#define CONFIG_SYS_CLKDIV_CPU 0
	42	/*
	43	* Set the HSB running at:
	44	* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
	45	*/
	46	#define CONFIG_SYS_CLKDIV_HSB 1
	47	/*
	48	* Set the PBA running at:
	49	* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
	50	*/
	51	#define CONFIG_SYS_CLKDIV_PBA 2
	52	/*
	53	* Set the PBB running at:
	54	* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
	55	*/
	56	#define CONFIG_SYS_CLKDIV_PBB 1
	57
	58	/* Reserve VM regions for NOR flash, NAND flash and SDRAM */
	59	#define CONFIG_SYS_NR_VM_REGIONS 3
	60
	61	/*
	62	* The PLLOPT register controls the PLL like this:
	63	* icp = PLLOPT<2>
	64	* ivco = PLLOPT<1:0>
	65	*
	66	* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
	67	*/
	68	#define CONFIG_SYS_PLL0_OPT 0x04
	69
	70	#define CONFIG_USART_BASE ATMEL_BASE_USART1
	71	#define CONFIG_USART_ID 1
	72
73	/* User serviceable stuff */
74	#define CONFIG_DOS_PARTITION
75
76	#define CONFIG_CMDLINE_TAG
77	#define CONFIG_SETUP_MEMORY_TAGS
78	#define CONFIG_INITRD_TAG
79
80	#define CONFIG_STACKSIZE (2048)
81
82	#define CONFIG_BAUDRATE 115200
83	#define CONFIG_BOOTARGS \
84	"root=mtd:main rootfstype=jffs2"
85	#define CONFIG_BOOTCOMMAND \
86	"fsload 0x10400000 /uImage; bootm"
87
88	/*
89	* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
90	* data on the serial line may interrupt the boot sequence.
91	*/
92	#define CONFIG_BOOTDELAY 1
93	#define CONFIG_AUTOBOOT
94	#define CONFIG_AUTOBOOT_KEYED
95	#define CONFIG_AUTOBOOT_PROMPT \
96	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
97	#define CONFIG_AUTOBOOT_DELAY_STR "d"
98	#define CONFIG_AUTOBOOT_STOP_STR " "
99
100	/*
101	* After booting the board for the first time, new ethernet addresses
102	* should be generated and assigned to the environment variables
103	* "ethaddr" and "eth1addr". This is normally done during production.
104	*/
105	#define CONFIG_OVERWRITE_ETHADDR_ONCE
106	#define CONFIG_NET_MULTI
107
108	/*
109	* BOOTP/DHCP options
110	*/
111	#define CONFIG_BOOTP_SUBNETMASK
112	#define CONFIG_BOOTP_GATEWAY
113
114	/*
115	* Command line configuration.
116	*/
117	#include <config_cmd_default.h>
118
119	#define CONFIG_CMD_ASKENV
120	#define CONFIG_CMD_DHCP
121	#define CONFIG_CMD_EXT2
122	#define CONFIG_CMD_FAT
123	#define CONFIG_CMD_JFFS2
124	#define CONFIG_CMD_MMC
125	#define CONFIG_CMD_SF
126	#define CONFIG_CMD_SPI
127	#define CONFIG_CMD_MII
128
129	#undef CONFIG_CMD_FPGA
130	#undef CONFIG_CMD_SETGETDCR
131	#undef CONFIG_CMD_XIMG
132
133	#define CONFIG_ATMEL_USART
134	#define CONFIG_MACB
135	#define CONFIG_PORTMUX_PIO
136	#define CONFIG_SYS_NR_PIOS 5
137	#define CONFIG_SYS_HSDRAMC
138	#define CONFIG_MMC
139	#define CONFIG_GENERIC_ATMEL_MCI
140	#define CONFIG_GENERIC_MMC
a420dfe2 AB	141	#define CONFIG_ATMEL_SPI
	142
	143	#define CONFIG_SPI_FLASH
	144	#define CONFIG_SPI_FLASH_ATMEL
	145
	146	#define CONFIG_SYS_DCACHE_LINESZ 32
	147	#define CONFIG_SYS_ICACHE_LINESZ 32
	148
	149	#define CONFIG_NR_DRAM_BANKS 1
	150
	151	#define CONFIG_SYS_FLASH_CFI
	152	#define CONFIG_FLASH_CFI_DRIVER
	153	#define CONFIG_SYS_FLASH_PROTECTION
	154
	155	#define CONFIG_SYS_FLASH_BASE 0x00000000
	156	#define CONFIG_SYS_FLASH_SIZE 0x800000
	157	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	158	#define CONFIG_SYS_MAX_FLASH_SECT 135
	159
	160	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	161
	162	#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
	163	#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
	164	#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
	165
	166	#define CONFIG_ENV_IS_IN_FLASH
	167	#define CONFIG_ENV_SIZE 65536
	168	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
	169
	170	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
	171
	172	#define CONFIG_SYS_MALLOC_LEN (256*1024)
	173	#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
	174
	175	/* Allow 4MB for the kernel run-time image */
	176	#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
	177	#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
	178
	179	/* Other configuration settings that shouldn't have to change all that often */
	180	#define CONFIG_SYS_PROMPT "U-Boot> "
	181	#define CONFIG_SYS_CBSIZE 256
	182	#define CONFIG_SYS_MAXARGS 16
	183	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	184	#define CONFIG_SYS_LONGHELP
	185
	186	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	187	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
	188
	189	#define CONFIG_MTD_DEVICE
	190	#define CONFIG_MTD_PARTITIONS
	191
	192	#endif /* __CONFIG_H */