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Commit | Line | Data |
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6ccec449 WD |
1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * Configuration settings for the ATSTK1002 CPU daughterboard | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
6ccec449 WD |
7 | */ |
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
5d73bc7a | 11 | #include <asm/arch/hardware.h> |
a23e277c | 12 | |
e3e8d463 AB |
13 | #define CONFIG_AVR32 |
14 | #define CONFIG_AT32AP | |
15 | #define CONFIG_AT32AP7000 | |
16 | #define CONFIG_ATSTK1002 | |
17 | #define CONFIG_ATSTK1000 | |
6ccec449 | 18 | |
6ccec449 WD |
19 | /* |
20 | * Timer clock frequency. We're using the CPU-internal COUNT register | |
21 | * for this, so this is equivalent to the CPU core clock frequency | |
22 | */ | |
6d0f6bcf | 23 | #define CONFIG_SYS_HZ 1000 |
6ccec449 WD |
24 | |
25 | /* | |
a4f3aab6 EA |
26 | * Set up the PLL to run at 140 MHz, the CPU to run at the PLL |
27 | * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the | |
28 | * PLL frequency. | |
6d0f6bcf | 29 | * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz |
6ccec449 | 30 | */ |
e3e8d463 AB |
31 | #define CONFIG_PLL |
32 | #define CONFIG_SYS_POWER_MANAGER | |
6d0f6bcf JCPV |
33 | #define CONFIG_SYS_OSC0_HZ 20000000 |
34 | #define CONFIG_SYS_PLL0_DIV 1 | |
35 | #define CONFIG_SYS_PLL0_MUL 7 | |
36 | #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 | |
a4f3aab6 EA |
37 | /* |
38 | * Set the CPU running at: | |
6d0f6bcf | 39 | * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz |
a4f3aab6 | 40 | */ |
6d0f6bcf | 41 | #define CONFIG_SYS_CLKDIV_CPU 0 |
a4f3aab6 EA |
42 | /* |
43 | * Set the HSB running at: | |
6d0f6bcf | 44 | * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz |
a4f3aab6 | 45 | */ |
6d0f6bcf | 46 | #define CONFIG_SYS_CLKDIV_HSB 1 |
a4f3aab6 EA |
47 | /* |
48 | * Set the PBA running at: | |
6d0f6bcf | 49 | * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz |
a4f3aab6 | 50 | */ |
6d0f6bcf | 51 | #define CONFIG_SYS_CLKDIV_PBA 2 |
a4f3aab6 EA |
52 | /* |
53 | * Set the PBB running at: | |
6d0f6bcf | 54 | * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz |
a4f3aab6 | 55 | */ |
6d0f6bcf | 56 | #define CONFIG_SYS_CLKDIV_PBB 1 |
6ccec449 | 57 | |
1f36f73f HS |
58 | /* Reserve VM regions for SDRAM and NOR flash */ |
59 | #define CONFIG_SYS_NR_VM_REGIONS 2 | |
60 | ||
6ccec449 WD |
61 | /* |
62 | * The PLLOPT register controls the PLL like this: | |
63 | * icp = PLLOPT<2> | |
64 | * ivco = PLLOPT<1:0> | |
65 | * | |
66 | * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). | |
67 | */ | |
6d0f6bcf | 68 | #define CONFIG_SYS_PLL0_OPT 0x04 |
6ccec449 | 69 | |
f4278b71 AB |
70 | #define CONFIG_USART_BASE ATMEL_BASE_USART1 |
71 | #define CONFIG_USART_ID 1 | |
6ccec449 WD |
72 | |
73 | /* User serviceable stuff */ | |
e3e8d463 | 74 | #define CONFIG_DOS_PARTITION |
8e687518 | 75 | |
e3e8d463 AB |
76 | #define CONFIG_CMDLINE_TAG |
77 | #define CONFIG_SETUP_MEMORY_TAGS | |
78 | #define CONFIG_INITRD_TAG | |
6ccec449 WD |
79 | |
80 | #define CONFIG_STACKSIZE (2048) | |
81 | ||
82 | #define CONFIG_BAUDRATE 115200 | |
83 | #define CONFIG_BOOTARGS \ | |
e80e585b | 84 | "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1" |
1b804b22 HS |
85 | |
86 | #define CONFIG_BOOTCOMMAND \ | |
87 | "fsload; bootm $(fileaddr)" | |
88 | ||
89 | /* | |
90 | * Only interrupt autoboot if <space> is pressed. Otherwise, garbage | |
91 | * data on the serial line may interrupt the boot sequence. | |
92 | */ | |
696dd130 | 93 | #define CONFIG_BOOTDELAY 1 |
e3e8d463 AB |
94 | #define CONFIG_AUTOBOOT |
95 | #define CONFIG_AUTOBOOT_KEYED | |
c37207d7 WD |
96 | #define CONFIG_AUTOBOOT_PROMPT \ |
97 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay | |
1b804b22 HS |
98 | #define CONFIG_AUTOBOOT_DELAY_STR "d" |
99 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
6ccec449 | 100 | |
9a24f477 | 101 | /* |
8b6684a6 HS |
102 | * After booting the board for the first time, new ethernet addresses |
103 | * should be generated and assigned to the environment variables | |
104 | * "ethaddr" and "eth1addr". This is normally done during production. | |
9a24f477 | 105 | */ |
e3e8d463 | 106 | #define CONFIG_OVERWRITE_ETHADDR_ONCE |
9a24f477 | 107 | |
2fd90ce5 JL |
108 | /* |
109 | * BOOTP options | |
110 | */ | |
111 | #define CONFIG_BOOTP_SUBNETMASK | |
112 | #define CONFIG_BOOTP_GATEWAY | |
113 | ||
6ccec449 | 114 | |
0b361c91 JL |
115 | /* |
116 | * Command line configuration. | |
117 | */ | |
118 | #include <config_cmd_default.h> | |
119 | ||
120 | #define CONFIG_CMD_ASKENV | |
121 | #define CONFIG_CMD_DHCP | |
122 | #define CONFIG_CMD_EXT2 | |
123 | #define CONFIG_CMD_FAT | |
124 | #define CONFIG_CMD_JFFS2 | |
125 | #define CONFIG_CMD_MMC | |
0b361c91 | 126 | |
55ac7a74 | 127 | #undef CONFIG_CMD_FPGA |
0b361c91 | 128 | #undef CONFIG_CMD_SETGETDCR |
74de7aef | 129 | #undef CONFIG_CMD_SOURCE |
0b361c91 JL |
130 | #undef CONFIG_CMD_XIMG |
131 | ||
e3e8d463 AB |
132 | #define CONFIG_ATMEL_USART |
133 | #define CONFIG_MACB | |
134 | #define CONFIG_PORTMUX_PIO | |
6d0f6bcf | 135 | #define CONFIG_SYS_NR_PIOS 5 |
e3e8d463 AB |
136 | #define CONFIG_SYS_HSDRAMC |
137 | #define CONFIG_MMC | |
72fa4679 SS |
138 | #define CONFIG_GENERIC_ATMEL_MCI |
139 | #define CONFIG_GENERIC_MMC | |
6ccec449 | 140 | |
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_DCACHE_LINESZ 32 |
142 | #define CONFIG_SYS_ICACHE_LINESZ 32 | |
6ccec449 WD |
143 | |
144 | #define CONFIG_NR_DRAM_BANKS 1 | |
145 | ||
22178652 AB |
146 | #define CONFIG_SYS_FLASH_CFI |
147 | #define CONFIG_FLASH_CFI_DRIVER | |
6ccec449 | 148 | |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_FLASH_BASE 0x00000000 |
150 | #define CONFIG_SYS_FLASH_SIZE 0x800000 | |
151 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
152 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
6ccec449 | 153 | |
6d0f6bcf | 154 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
47293c18 | 155 | #define CONFIG_SYS_TEXT_BASE 0x00000000 |
6ccec449 | 156 | |
6d0f6bcf JCPV |
157 | #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE |
158 | #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE | |
159 | #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE | |
6ccec449 | 160 | |
e3e8d463 | 161 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 162 | #define CONFIG_ENV_SIZE 65536 |
6d0f6bcf | 163 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) |
6ccec449 | 164 | |
6d0f6bcf | 165 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) |
6ccec449 | 166 | |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_MALLOC_LEN (256*1024) |
168 | #define CONFIG_SYS_DMA_ALLOC_LEN (16384) | |
1f4f2121 | 169 | |
8269ab53 | 170 | /* Allow 4MB for the kernel run-time image */ |
6d0f6bcf JCPV |
171 | #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) |
172 | #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) | |
6ccec449 WD |
173 | |
174 | /* Other configuration settings that shouldn't have to change all that often */ | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_PROMPT "U-Boot> " |
176 | #define CONFIG_SYS_CBSIZE 256 | |
177 | #define CONFIG_SYS_MAXARGS 16 | |
178 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
e3e8d463 | 179 | #define CONFIG_SYS_LONGHELP |
6d0f6bcf JCPV |
180 | |
181 | #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE | |
182 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) | |
183 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } | |
6ccec449 WD |
184 | |
185 | #endif /* __CONFIG_H */ |