[people/ms/u-boot.git] / include / configs / atstk1003.h

/*
 * Copyright (C) 2007 Atmel Corporation
 *
 * Configuration settings for the ATSTK1003 CPU daughterboard
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/hardware.h>

#define CONFIG_AT32AP
#define CONFIG_AT32AP7001
#define CONFIG_ATSTK1003
#define CONFIG_ATSTK1000

/*
 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
 * PLL frequency.
 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
 */
#define CONFIG_PLL
#define CONFIG_SYS_POWER_MANAGER
#define CONFIG_SYS_OSC0_HZ			20000000
#define CONFIG_SYS_PLL0_DIV			1
#define CONFIG_SYS_PLL0_MUL			7
#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
/*
 * Set the CPU running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
 */
#define CONFIG_SYS_CLKDIV_CPU			0
/*
 * Set the HSB running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
 */
#define CONFIG_SYS_CLKDIV_HSB			1
/*
 * Set the PBA running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
 */
#define CONFIG_SYS_CLKDIV_PBA			2
/*
 * Set the PBB running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
 */
#define CONFIG_SYS_CLKDIV_PBB			1

/* Reserve VM regions for SDRAM and NOR flash */
#define CONFIG_SYS_NR_VM_REGIONS		2

/*
 * The PLLOPT register controls the PLL like this:
 *   icp = PLLOPT<2>
 *   ivco = PLLOPT<1:0>
 *
 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
 */
#define CONFIG_SYS_PLL0_OPT			0x04

#define CONFIG_USART_BASE		ATMEL_BASE_USART1
#define CONFIG_USART_ID			1

/* User serviceable stuff */
#define CONFIG_DOS_PARTITION

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

#define CONFIG_STACKSIZE		(2048)

#define CONFIG_BAUDRATE			115200
#define CONFIG_BOOTARGS							\
	"console=ttyS0 root=/dev/mmcblk0p1 rootwait"

#define CONFIG_BOOTCOMMAND						\
	"mmc rescan; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm"

/*
 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
 * data on the serial line may interrupt the boot sequence.
 */
#define CONFIG_BOOTDELAY		1
#define CONFIG_AUTOBOOT
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT		\
	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR	"d"
#define CONFIG_AUTOBOOT_STOP_STR	" "

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC

#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG

#define CONFIG_ATMEL_USART
#define CONFIG_PORTMUX_PIO
#define CONFIG_SYS_HSDRAMC
#define CONFIG_MMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_GENERIC_MMC

#define CONFIG_SYS_DCACHE_LINESZ		32
#define CONFIG_SYS_ICACHE_LINESZ		32

#define CONFIG_NR_DRAM_BANKS		1

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER

#define CONFIG_SYS_FLASH_BASE			0x00000000
#define CONFIG_SYS_FLASH_SIZE			0x800000
#define CONFIG_SYS_MAX_FLASH_BANKS		1
#define CONFIG_SYS_MAX_FLASH_SECT		135

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_TEXT_BASE		0x00000000

#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE			65536
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)

#define CONFIG_SYS_MALLOC_LEN			(256*1024)

/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)

/* Other configuration settings that shouldn't have to change all that often */
#define CONFIG_SYS_PROMPT			"U-Boot> "
#define CONFIG_SYS_CBSIZE			256
#define CONFIG_SYS_MAXARGS			16
#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP

#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x700000)
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }

#endif /* __CONFIG_H */
Commit	Line	Data
667568db HS	1	/*
	2	* Copyright (C) 2007 Atmel Corporation
	3	*
	4	* Configuration settings for the ATSTK1003 CPU daughterboard
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
667568db HS	7	*/
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
5d73bc7a	11	#include <asm/arch/hardware.h>
a23e277c	12
38a39398 AB	13	#define CONFIG_AT32AP
	14	#define CONFIG_AT32AP7001
	15	#define CONFIG_ATSTK1003
	16	#define CONFIG_ATSTK1000
667568db	17
667568db HS	18	/*
	19	* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
	20	* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
	21	* PLL frequency.
6d0f6bcf	22	* (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
667568db	23	*/
38a39398 AB	24	#define CONFIG_PLL
38a39398 AB	25	#define CONFIG_SYS_POWER_MANAGER
6d0f6bcf JCPV	26	#define CONFIG_SYS_OSC0_HZ 20000000
	27	#define CONFIG_SYS_PLL0_DIV 1
	28	#define CONFIG_SYS_PLL0_MUL 7
	29	#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
667568db HS	30	/*
667568db HS	31	* Set the CPU running at:
6d0f6bcf	32	* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
667568db	33	*/
6d0f6bcf	34	#define CONFIG_SYS_CLKDIV_CPU 0
667568db HS	35	/*
667568db HS	36	* Set the HSB running at:
6d0f6bcf	37	* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
667568db	38	*/
6d0f6bcf	39	#define CONFIG_SYS_CLKDIV_HSB 1
667568db HS	40	/*
667568db HS	41	* Set the PBA running at:
6d0f6bcf	42	* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
667568db	43	*/
6d0f6bcf	44	#define CONFIG_SYS_CLKDIV_PBA 2
667568db HS	45	/*
667568db HS	46	* Set the PBB running at:
6d0f6bcf	47	* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
667568db	48	*/
6d0f6bcf	49	#define CONFIG_SYS_CLKDIV_PBB 1
667568db	50
1f36f73f HS	51	/* Reserve VM regions for SDRAM and NOR flash */
	52	#define CONFIG_SYS_NR_VM_REGIONS 2
	53
667568db HS	54	/*
	55	* The PLLOPT register controls the PLL like this:
	56	* icp = PLLOPT<2>
	57	* ivco = PLLOPT<1:0>
	58	*
	59	* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
	60	*/
6d0f6bcf	61	#define CONFIG_SYS_PLL0_OPT 0x04
667568db	62
f4278b71 AB	63	#define CONFIG_USART_BASE ATMEL_BASE_USART1
f4278b71 AB	64	#define CONFIG_USART_ID 1
667568db HS	65
667568db HS	66	/* User serviceable stuff */
38a39398	67	#define CONFIG_DOS_PARTITION
667568db	68
38a39398 AB	69	#define CONFIG_CMDLINE_TAG
	70	#define CONFIG_SETUP_MEMORY_TAGS
	71	#define CONFIG_INITRD_TAG
667568db HS	72
	73	#define CONFIG_STACKSIZE (2048)
	74
	75	#define CONFIG_BAUDRATE 115200
	76	#define CONFIG_BOOTARGS \
	77	"console=ttyS0 root=/dev/mmcblk0p1 rootwait"
	78
	79	#define CONFIG_BOOTCOMMAND \
72fa4679	80	"mmc rescan; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm"
667568db HS	81
	82	/*
	83	* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
	84	* data on the serial line may interrupt the boot sequence.
	85	*/
	86	#define CONFIG_BOOTDELAY 1
38a39398 AB	87	#define CONFIG_AUTOBOOT
38a39398 AB	88	#define CONFIG_AUTOBOOT_KEYED
c37207d7 WD	89	#define CONFIG_AUTOBOOT_PROMPT \
c37207d7 WD	90	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
667568db HS	91	#define CONFIG_AUTOBOOT_DELAY_STR "d"
	92	#define CONFIG_AUTOBOOT_STOP_STR " "
	93
	94	/*
	95	* Command line configuration.
	96	*/
	97	#include <config_cmd_default.h>
	98
	99	#define CONFIG_CMD_ASKENV
	100	#define CONFIG_CMD_EXT2
	101	#define CONFIG_CMD_FAT
	102	#define CONFIG_CMD_JFFS2
	103	#define CONFIG_CMD_MMC
	104
	105	#undef CONFIG_CMD_FPGA
	106	#undef CONFIG_CMD_NET
	107	#undef CONFIG_CMD_NFS
	108	#undef CONFIG_CMD_SETGETDCR
	109	#undef CONFIG_CMD_XIMG
	110
38a39398 AB	111	#define CONFIG_ATMEL_USART
	112	#define CONFIG_PORTMUX_PIO
	113	#define CONFIG_SYS_HSDRAMC
	114	#define CONFIG_MMC
72fa4679 SS	115	#define CONFIG_GENERIC_ATMEL_MCI
72fa4679 SS	116	#define CONFIG_GENERIC_MMC
667568db	117
6d0f6bcf JCPV	118	#define CONFIG_SYS_DCACHE_LINESZ 32
6d0f6bcf JCPV	119	#define CONFIG_SYS_ICACHE_LINESZ 32
667568db HS	120
	121	#define CONFIG_NR_DRAM_BANKS 1
	122
22178652 AB	123	#define CONFIG_SYS_FLASH_CFI
22178652 AB	124	#define CONFIG_FLASH_CFI_DRIVER
667568db	125
6d0f6bcf JCPV	126	#define CONFIG_SYS_FLASH_BASE 0x00000000
	127	#define CONFIG_SYS_FLASH_SIZE 0x800000
	128	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	129	#define CONFIG_SYS_MAX_FLASH_SECT 135
667568db	130
6d0f6bcf	131	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
47293c18	132	#define CONFIG_SYS_TEXT_BASE 0x00000000
667568db	133
6d0f6bcf JCPV	134	#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
	135	#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
	136	#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
667568db	137
38a39398	138	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586	139	#define CONFIG_ENV_SIZE 65536
6d0f6bcf	140	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
667568db	141
6d0f6bcf	142	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
667568db	143
6d0f6bcf	144	#define CONFIG_SYS_MALLOC_LEN (256*1024)
667568db HS	145
667568db HS	146	/* Allow 4MB for the kernel run-time image */
6d0f6bcf JCPV	147	#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
6d0f6bcf JCPV	148	#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
667568db HS	149
667568db HS	150	/* Other configuration settings that shouldn't have to change all that often */
6d0f6bcf JCPV	151	#define CONFIG_SYS_PROMPT "U-Boot> "
	152	#define CONFIG_SYS_CBSIZE 256
	153	#define CONFIG_SYS_MAXARGS 16
	154	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
38a39398	155	#define CONFIG_SYS_LONGHELP
6d0f6bcf JCPV	156
	157	#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
	158	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
	159	#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
667568db HS	160
667568db HS	161	#endif /* __CONFIG_H */