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667568db HS |
1 | /* |
2 | * Copyright (C) 2007 Atmel Corporation | |
3 | * | |
4 | * Configuration settings for the ATSTK1003 CPU daughterboard | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
5d73bc7a | 27 | #include <asm/arch/hardware.h> |
a23e277c | 28 | |
38a39398 AB |
29 | #define CONFIG_AVR32 |
30 | #define CONFIG_AT32AP | |
31 | #define CONFIG_AT32AP7001 | |
32 | #define CONFIG_ATSTK1003 | |
33 | #define CONFIG_ATSTK1000 | |
667568db | 34 | |
667568db HS |
35 | /* |
36 | * Timer clock frequency. We're using the CPU-internal COUNT register | |
37 | * for this, so this is equivalent to the CPU core clock frequency | |
38 | */ | |
6d0f6bcf | 39 | #define CONFIG_SYS_HZ 1000 |
667568db HS |
40 | |
41 | /* | |
42 | * Set up the PLL to run at 140 MHz, the CPU to run at the PLL | |
43 | * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the | |
44 | * PLL frequency. | |
6d0f6bcf | 45 | * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz |
667568db | 46 | */ |
38a39398 AB |
47 | #define CONFIG_PLL |
48 | #define CONFIG_SYS_POWER_MANAGER | |
6d0f6bcf JCPV |
49 | #define CONFIG_SYS_OSC0_HZ 20000000 |
50 | #define CONFIG_SYS_PLL0_DIV 1 | |
51 | #define CONFIG_SYS_PLL0_MUL 7 | |
52 | #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 | |
667568db HS |
53 | /* |
54 | * Set the CPU running at: | |
6d0f6bcf | 55 | * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz |
667568db | 56 | */ |
6d0f6bcf | 57 | #define CONFIG_SYS_CLKDIV_CPU 0 |
667568db HS |
58 | /* |
59 | * Set the HSB running at: | |
6d0f6bcf | 60 | * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz |
667568db | 61 | */ |
6d0f6bcf | 62 | #define CONFIG_SYS_CLKDIV_HSB 1 |
667568db HS |
63 | /* |
64 | * Set the PBA running at: | |
6d0f6bcf | 65 | * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz |
667568db | 66 | */ |
6d0f6bcf | 67 | #define CONFIG_SYS_CLKDIV_PBA 2 |
667568db HS |
68 | /* |
69 | * Set the PBB running at: | |
6d0f6bcf | 70 | * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz |
667568db | 71 | */ |
6d0f6bcf | 72 | #define CONFIG_SYS_CLKDIV_PBB 1 |
667568db | 73 | |
1f36f73f HS |
74 | /* Reserve VM regions for SDRAM and NOR flash */ |
75 | #define CONFIG_SYS_NR_VM_REGIONS 2 | |
76 | ||
667568db HS |
77 | /* |
78 | * The PLLOPT register controls the PLL like this: | |
79 | * icp = PLLOPT<2> | |
80 | * ivco = PLLOPT<1:0> | |
81 | * | |
82 | * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). | |
83 | */ | |
6d0f6bcf | 84 | #define CONFIG_SYS_PLL0_OPT 0x04 |
667568db | 85 | |
f4278b71 AB |
86 | #define CONFIG_USART_BASE ATMEL_BASE_USART1 |
87 | #define CONFIG_USART_ID 1 | |
667568db HS |
88 | |
89 | /* User serviceable stuff */ | |
38a39398 | 90 | #define CONFIG_DOS_PARTITION |
667568db | 91 | |
38a39398 AB |
92 | #define CONFIG_CMDLINE_TAG |
93 | #define CONFIG_SETUP_MEMORY_TAGS | |
94 | #define CONFIG_INITRD_TAG | |
667568db HS |
95 | |
96 | #define CONFIG_STACKSIZE (2048) | |
97 | ||
98 | #define CONFIG_BAUDRATE 115200 | |
99 | #define CONFIG_BOOTARGS \ | |
100 | "console=ttyS0 root=/dev/mmcblk0p1 rootwait" | |
101 | ||
102 | #define CONFIG_BOOTCOMMAND \ | |
103 | "mmcinit; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm" | |
104 | ||
105 | /* | |
106 | * Only interrupt autoboot if <space> is pressed. Otherwise, garbage | |
107 | * data on the serial line may interrupt the boot sequence. | |
108 | */ | |
109 | #define CONFIG_BOOTDELAY 1 | |
38a39398 AB |
110 | #define CONFIG_AUTOBOOT |
111 | #define CONFIG_AUTOBOOT_KEYED | |
c37207d7 WD |
112 | #define CONFIG_AUTOBOOT_PROMPT \ |
113 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay | |
667568db HS |
114 | #define CONFIG_AUTOBOOT_DELAY_STR "d" |
115 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
116 | ||
117 | /* | |
118 | * Command line configuration. | |
119 | */ | |
120 | #include <config_cmd_default.h> | |
121 | ||
122 | #define CONFIG_CMD_ASKENV | |
123 | #define CONFIG_CMD_EXT2 | |
124 | #define CONFIG_CMD_FAT | |
125 | #define CONFIG_CMD_JFFS2 | |
126 | #define CONFIG_CMD_MMC | |
127 | ||
128 | #undef CONFIG_CMD_FPGA | |
129 | #undef CONFIG_CMD_NET | |
130 | #undef CONFIG_CMD_NFS | |
131 | #undef CONFIG_CMD_SETGETDCR | |
132 | #undef CONFIG_CMD_XIMG | |
133 | ||
38a39398 AB |
134 | #define CONFIG_ATMEL_USART |
135 | #define CONFIG_PORTMUX_PIO | |
136 | #define CONFIG_SYS_HSDRAMC | |
137 | #define CONFIG_MMC | |
138 | #define CONFIG_ATMEL_MCI | |
667568db | 139 | |
6d0f6bcf JCPV |
140 | #define CONFIG_SYS_DCACHE_LINESZ 32 |
141 | #define CONFIG_SYS_ICACHE_LINESZ 32 | |
667568db HS |
142 | |
143 | #define CONFIG_NR_DRAM_BANKS 1 | |
144 | ||
22178652 AB |
145 | #define CONFIG_SYS_FLASH_CFI |
146 | #define CONFIG_FLASH_CFI_DRIVER | |
667568db | 147 | |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_FLASH_BASE 0x00000000 |
149 | #define CONFIG_SYS_FLASH_SIZE 0x800000 | |
150 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
151 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
667568db | 152 | |
6d0f6bcf | 153 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
47293c18 | 154 | #define CONFIG_SYS_TEXT_BASE 0x00000000 |
667568db | 155 | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE |
157 | #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE | |
158 | #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE | |
667568db | 159 | |
38a39398 | 160 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 161 | #define CONFIG_ENV_SIZE 65536 |
6d0f6bcf | 162 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) |
667568db | 163 | |
6d0f6bcf | 164 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) |
667568db | 165 | |
6d0f6bcf | 166 | #define CONFIG_SYS_MALLOC_LEN (256*1024) |
667568db HS |
167 | |
168 | /* Allow 4MB for the kernel run-time image */ | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) |
170 | #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) | |
667568db HS |
171 | |
172 | /* Other configuration settings that shouldn't have to change all that often */ | |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_PROMPT "U-Boot> " |
174 | #define CONFIG_SYS_CBSIZE 256 | |
175 | #define CONFIG_SYS_MAXARGS 16 | |
176 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
38a39398 | 177 | #define CONFIG_SYS_LONGHELP |
6d0f6bcf JCPV |
178 | |
179 | #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE | |
180 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) | |
181 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } | |
667568db HS |
182 | |
183 | #endif /* __CONFIG_H */ |