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1 | /* |
2 | * Copyright (C) 2007 Atmel Corporation | |
3 | * | |
4 | * Configuration settings for the ATSTK1003 CPU daughterboard | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | #define CONFIG_AVR32 1 | |
28 | #define CONFIG_AT32AP 1 | |
29 | #define CONFIG_AT32AP7001 1 | |
30 | #define CONFIG_ATSTK1003 1 | |
31 | #define CONFIG_ATSTK1000 1 | |
32 | ||
33 | #define CONFIG_ATSTK1000_EXT_FLASH 1 | |
34 | ||
35 | /* | |
36 | * Timer clock frequency. We're using the CPU-internal COUNT register | |
37 | * for this, so this is equivalent to the CPU core clock frequency | |
38 | */ | |
39 | #define CFG_HZ 1000 | |
40 | ||
41 | /* | |
42 | * Set up the PLL to run at 140 MHz, the CPU to run at the PLL | |
43 | * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the | |
44 | * PLL frequency. | |
45 | * (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz | |
46 | */ | |
47 | #define CONFIG_PLL 1 | |
48 | #define CFG_POWER_MANAGER 1 | |
49 | #define CFG_OSC0_HZ 20000000 | |
50 | #define CFG_PLL0_DIV 1 | |
51 | #define CFG_PLL0_MUL 7 | |
52 | #define CFG_PLL0_SUPPRESS_CYCLES 16 | |
53 | /* | |
54 | * Set the CPU running at: | |
55 | * PLL / (2^CFG_CLKDIV_CPU) = CPU MHz | |
56 | */ | |
57 | #define CFG_CLKDIV_CPU 0 | |
58 | /* | |
59 | * Set the HSB running at: | |
60 | * PLL / (2^CFG_CLKDIV_HSB) = HSB MHz | |
61 | */ | |
62 | #define CFG_CLKDIV_HSB 1 | |
63 | /* | |
64 | * Set the PBA running at: | |
65 | * PLL / (2^CFG_CLKDIV_PBA) = PBA MHz | |
66 | */ | |
67 | #define CFG_CLKDIV_PBA 2 | |
68 | /* | |
69 | * Set the PBB running at: | |
70 | * PLL / (2^CFG_CLKDIV_PBB) = PBB MHz | |
71 | */ | |
72 | #define CFG_CLKDIV_PBB 1 | |
73 | ||
74 | /* | |
75 | * The PLLOPT register controls the PLL like this: | |
76 | * icp = PLLOPT<2> | |
77 | * ivco = PLLOPT<1:0> | |
78 | * | |
79 | * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). | |
80 | */ | |
81 | #define CFG_PLL0_OPT 0x04 | |
82 | ||
83 | #undef CONFIG_USART0 | |
84 | #define CONFIG_USART1 1 | |
85 | #undef CONFIG_USART2 | |
86 | #undef CONFIG_USART3 | |
87 | ||
88 | /* User serviceable stuff */ | |
89 | #define CONFIG_DOS_PARTITION 1 | |
90 | ||
91 | #define CONFIG_CMDLINE_TAG 1 | |
92 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
93 | #define CONFIG_INITRD_TAG 1 | |
94 | ||
95 | #define CONFIG_STACKSIZE (2048) | |
96 | ||
97 | #define CONFIG_BAUDRATE 115200 | |
98 | #define CONFIG_BOOTARGS \ | |
99 | "console=ttyS0 root=/dev/mmcblk0p1 rootwait" | |
100 | ||
101 | #define CONFIG_BOOTCOMMAND \ | |
102 | "mmcinit; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm" | |
103 | ||
104 | /* | |
105 | * Only interrupt autoboot if <space> is pressed. Otherwise, garbage | |
106 | * data on the serial line may interrupt the boot sequence. | |
107 | */ | |
108 | #define CONFIG_BOOTDELAY 1 | |
109 | #define CONFIG_AUTOBOOT 1 | |
110 | #define CONFIG_AUTOBOOT_KEYED 1 | |
111 | #define CONFIG_AUTOBOOT_PROMPT \ | |
112 | "Press SPACE to abort autoboot in %d seconds\n" | |
113 | #define CONFIG_AUTOBOOT_DELAY_STR "d" | |
114 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
115 | ||
116 | /* | |
117 | * Command line configuration. | |
118 | */ | |
119 | #include <config_cmd_default.h> | |
120 | ||
121 | #define CONFIG_CMD_ASKENV | |
122 | #define CONFIG_CMD_EXT2 | |
123 | #define CONFIG_CMD_FAT | |
124 | #define CONFIG_CMD_JFFS2 | |
125 | #define CONFIG_CMD_MMC | |
126 | ||
127 | #undef CONFIG_CMD_FPGA | |
128 | #undef CONFIG_CMD_NET | |
129 | #undef CONFIG_CMD_NFS | |
130 | #undef CONFIG_CMD_SETGETDCR | |
131 | #undef CONFIG_CMD_XIMG | |
132 | ||
133 | #define CONFIG_ATMEL_USART 1 | |
134 | #define CONFIG_PIO2 1 | |
135 | #define CFG_HSDRAMC 1 | |
136 | #define CONFIG_MMC 1 | |
137 | ||
138 | #define CFG_DCACHE_LINESZ 32 | |
139 | #define CFG_ICACHE_LINESZ 32 | |
140 | ||
141 | #define CONFIG_NR_DRAM_BANKS 1 | |
142 | ||
143 | /* External flash on STK1000 */ | |
144 | #if 0 | |
145 | #define CFG_FLASH_CFI 1 | |
146 | #define CFG_FLASH_CFI_DRIVER 1 | |
147 | #endif | |
148 | ||
149 | #define CFG_FLASH_BASE 0x00000000 | |
150 | #define CFG_FLASH_SIZE 0x800000 | |
151 | #define CFG_MAX_FLASH_BANKS 1 | |
152 | #define CFG_MAX_FLASH_SECT 135 | |
153 | ||
154 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
155 | ||
156 | #define CFG_INTRAM_BASE 0x24000000 | |
157 | #define CFG_INTRAM_SIZE 0x8000 | |
158 | ||
159 | #define CFG_SDRAM_BASE 0x10000000 | |
160 | ||
161 | #define CFG_ENV_IS_IN_FLASH 1 | |
162 | #define CFG_ENV_SIZE 65536 | |
163 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) | |
164 | ||
165 | #define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) | |
166 | ||
167 | #define CFG_MALLOC_LEN (256*1024) | |
168 | ||
169 | /* Allow 4MB for the kernel run-time image */ | |
170 | #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000) | |
171 | #define CFG_BOOTPARAMS_LEN (16 * 1024) | |
172 | ||
173 | /* Other configuration settings that shouldn't have to change all that often */ | |
55ac7a74 | 174 | #define CFG_PROMPT "U-Boot> " |
667568db HS |
175 | #define CFG_CBSIZE 256 |
176 | #define CFG_MAXARGS 16 | |
177 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) | |
178 | #define CFG_LONGHELP 1 | |
179 | ||
180 | #define CFG_MEMTEST_START CFG_SDRAM_BASE | |
181 | #define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x700000) | |
182 | #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } | |
183 | ||
184 | #endif /* __CONFIG_H */ |