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8a316c9b | 1 | /* |
8b39501d | 2 | * (C) Copyright 2005-2007 |
8a316c9b SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /************************************************************************ | |
25 | * bamboo.h - configuration for BAMBOO board | |
26 | ***********************************************************************/ | |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /*----------------------------------------------------------------------- | |
31 | * High Level Configuration Options | |
32 | *----------------------------------------------------------------------*/ | |
17f50f22 | 33 | #define CONFIG_BAMBOO 1 /* Board is BAMBOO */ |
846b0dd2 | 34 | #define CONFIG_440EP 1 /* Specific PPC440EP support */ |
efa35cf1 | 35 | #define CONFIG_440 1 /* ... PPC440 family */ |
17f50f22 | 36 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
8a316c9b SR |
37 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
38 | ||
490f2040 SR |
39 | /* |
40 | * Include common defines/options for all AMCC eval boards | |
41 | */ | |
42 | #define CONFIG_HOSTNAME bamboo | |
43 | #include "amcc-common.h" | |
44 | ||
c57c7980 SR |
45 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
46 | ||
47 | /* | |
48 | * Please note that, if NAND support is enabled, the 2nd ethernet port | |
49 | * can't be used because of pin multiplexing. So, if you want to use the | |
50 | * 2nd ethernet port you have to "undef" the following define. | |
51 | */ | |
52 | #define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */ | |
53 | ||
8a316c9b SR |
54 | /*----------------------------------------------------------------------- |
55 | * Base addresses -- Note these are effective addresses where the | |
56 | * actual resources get mapped (not physical addresses) | |
57 | *----------------------------------------------------------------------*/ | |
17f50f22 SR |
58 | #define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ |
59 | #define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ | |
60 | #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 | |
61 | #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 | |
62 | #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 | |
8a316c9b SR |
63 | |
64 | /*Don't change either of these*/ | |
17f50f22 SR |
65 | #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ |
66 | #define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/ | |
8a316c9b SR |
67 | /*Don't change either of these*/ |
68 | ||
17f50f22 SR |
69 | #define CFG_USB_DEVICE 0x50000000 |
70 | #define CFG_NVRAM_BASE_ADDR 0x80000000 | |
c57c7980 SR |
71 | #define CFG_BOOT_BASE_ADDR 0xf0000000 |
72 | #define CFG_NAND_ADDR 0x90000000 | |
73 | #define CFG_NAND2_ADDR 0x94000000 | |
8a316c9b SR |
74 | |
75 | /*----------------------------------------------------------------------- | |
76 | * Initial RAM & stack pointer (placed in SDRAM) | |
77 | *----------------------------------------------------------------------*/ | |
887e2ec9 | 78 | #define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
1636d1c8 | 79 | #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ |
3d9569b2 | 80 | #define CFG_INIT_RAM_END (4 << 10) |
1636d1c8 | 81 | #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ |
8a316c9b SR |
82 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
83 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
84 | ||
8a316c9b SR |
85 | /*----------------------------------------------------------------------- |
86 | * Serial Port | |
87 | *----------------------------------------------------------------------*/ | |
88 | #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ | |
17f50f22 | 89 | /* define this if you want console on UART1 */ |
8a316c9b SR |
90 | #undef CONFIG_UART1_CONSOLE |
91 | ||
8a316c9b SR |
92 | /*----------------------------------------------------------------------- |
93 | * NVRAM/RTC | |
94 | * | |
95 | * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF | |
96 | * The DS1558 code assumes this condition | |
97 | * | |
98 | *----------------------------------------------------------------------*/ | |
c57c7980 | 99 | #define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ |
17f50f22 SR |
100 | #define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ |
101 | ||
102 | /*----------------------------------------------------------------------- | |
103 | * Environment | |
104 | *----------------------------------------------------------------------*/ | |
cf959c7d | 105 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
17f50f22 SR |
106 | #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
107 | #else | |
cf959c7d SR |
108 | #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ |
109 | #define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ | |
17f50f22 | 110 | #endif |
8a316c9b SR |
111 | |
112 | /*----------------------------------------------------------------------- | |
113 | * FLASH related | |
114 | *----------------------------------------------------------------------*/ | |
1636d1c8 WD |
115 | #define CFG_MAX_FLASH_BANKS 3 /* number of banks */ |
116 | #define CFG_MAX_FLASH_SECT 256 /* sectors per device */ | |
8a316c9b SR |
117 | |
118 | #undef CFG_FLASH_CHECKSUM | |
119 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
17f50f22 | 120 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
8a316c9b | 121 | |
17f50f22 SR |
122 | #define CFG_FLASH_ADDR0 0x555 |
123 | #define CFG_FLASH_ADDR1 0x2aa | |
124 | #define CFG_FLASH_WORD_SIZE unsigned char | |
8a316c9b | 125 | |
1636d1c8 WD |
126 | #define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ |
127 | #define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ | |
8a316c9b | 128 | |
17f50f22 | 129 | #ifdef CFG_ENV_IS_IN_FLASH |
1636d1c8 | 130 | #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
cf959c7d | 131 | #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) |
c57c7980 | 132 | #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
17f50f22 | 133 | |
17f50f22 SR |
134 | /* Address and size of Redundant Environment Sector */ |
135 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) | |
136 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
17f50f22 | 137 | #endif /* CFG_ENV_IS_IN_FLASH */ |
8a316c9b | 138 | |
cf959c7d SR |
139 | /* |
140 | * IPL (Initial Program Loader, integrated inside CPU) | |
141 | * Will load first 4k from NAND (SPL) into cache and execute it from there. | |
142 | * | |
143 | * SPL (Secondary Program Loader) | |
144 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL | |
145 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM | |
146 | * controller and the NAND controller so that the special U-Boot image can be | |
147 | * loaded from NAND to SDRAM. | |
148 | * | |
149 | * NUB (NAND U-Boot) | |
150 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started | |
151 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. | |
152 | * | |
153 | * On 440EPx the SPL is copied to SDRAM before the NAND controller is | |
154 | * set up. While still running from cache, I experienced problems accessing | |
155 | * the NAND controller. sr - 2006-08-25 | |
156 | */ | |
157 | #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ | |
158 | #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ | |
159 | #define CFG_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */ | |
160 | #define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ | |
161 | #define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ | |
162 | #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) | |
163 | ||
164 | /* | |
165 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) | |
166 | */ | |
167 | #define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ | |
168 | #define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ | |
169 | ||
170 | /* | |
171 | * Now the NAND chip has to be defined (no autodetection used!) | |
172 | */ | |
173 | #define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */ | |
174 | #define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
175 | #define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */ | |
176 | #define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ | |
177 | #define CFG_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */ | |
178 | ||
179 | #define CFG_NAND_ECCSIZE 256 | |
180 | #define CFG_NAND_ECCBYTES 3 | |
181 | #define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) | |
182 | #define CFG_NAND_OOBSIZE 16 | |
183 | #define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) | |
184 | #define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} | |
185 | ||
186 | #ifdef CFG_ENV_IS_IN_NAND | |
187 | /* | |
188 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
189 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. | |
190 | */ | |
191 | #define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE | |
192 | #define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) | |
193 | #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) | |
194 | #endif | |
195 | ||
c57c7980 | 196 | /*----------------------------------------------------------------------- |
8b39501d | 197 | * NAND FLASH |
c57c7980 | 198 | *----------------------------------------------------------------------*/ |
cf959c7d SR |
199 | #define CFG_MAX_NAND_DEVICE 2 |
200 | #define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE | |
8b39501d | 201 | #define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) |
cf959c7d | 202 | #define CFG_NAND_BASE_LIST { CFG_NAND_BASE, CFG_NAND_ADDR + 2 } |
8b39501d | 203 | #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ |
c57c7980 | 204 | |
cf959c7d SR |
205 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
206 | #define CFG_NAND_CS 1 | |
207 | #else | |
208 | #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ | |
209 | /* Memory Bank 0 (NAND-FLASH) initialization */ | |
210 | #define CFG_EBC_PB0AP 0x018003c0 | |
211 | #define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000) | |
212 | #endif | |
213 | ||
8a316c9b SR |
214 | /*----------------------------------------------------------------------- |
215 | * DDR SDRAM | |
17f50f22 SR |
216 | *----------------------------------------------------------------------------- */ |
217 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ | |
fd49bf02 SR |
218 | #undef CONFIG_DDR_ECC /* don't use ECC */ |
219 | #define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */ | |
cf959c7d SR |
220 | #define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51} |
221 | #define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */ | |
d2f68006 | 222 | #define CONFIG_PROG_SDRAM_TLB |
8a316c9b SR |
223 | |
224 | /*----------------------------------------------------------------------- | |
225 | * I2C | |
226 | *----------------------------------------------------------------------*/ | |
8a316c9b | 227 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
8a316c9b | 228 | |
8a316c9b | 229 | #define CFG_I2C_MULTI_EEPROMS |
8a316c9b SR |
230 | #define CFG_I2C_EEPROM_ADDR (0xa8>>1) |
231 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
232 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
233 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 | |
234 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
235 | ||
17f50f22 SR |
236 | #ifdef CFG_ENV_IS_IN_EEPROM |
237 | #define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ | |
238 | #define CFG_ENV_OFFSET 0x0 | |
239 | #endif /* CFG_ENV_IS_IN_EEPROM */ | |
240 | ||
490f2040 SR |
241 | /* |
242 | * Default environment variables | |
243 | */ | |
17f50f22 | 244 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
490f2040 SR |
245 | CONFIG_AMCC_DEF_ENV \ |
246 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
247 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
248 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
249 | CONFIG_AMCC_DEF_ENV_NAND_UPD \ | |
17f50f22 SR |
250 | "kernel_addr=fff00000\0" \ |
251 | "ramdisk_addr=fff10000\0" \ | |
17f50f22 | 252 | "" |
8a316c9b | 253 | |
a00eccfe | 254 | #define CONFIG_HAS_ETH0 |
17f50f22 | 255 | #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ |
d6c61aab | 256 | #define CONFIG_PHY1_ADDR 1 |
c57c7980 SR |
257 | |
258 | #ifndef CONFIG_BAMBOO_NAND | |
8a316c9b | 259 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
c57c7980 SR |
260 | #endif /* CONFIG_BAMBOO_NAND */ |
261 | ||
846b0dd2 | 262 | #ifdef CONFIG_440EP |
8a316c9b SR |
263 | /* USB */ |
264 | #define CONFIG_USB_OHCI | |
265 | #define CONFIG_USB_STORAGE | |
266 | ||
267 | /*Comment this out to enable USB 1.1 device*/ | |
268 | #define USB_2_0_DEVICE | |
846b0dd2 | 269 | #endif /*CONFIG_440EP*/ |
8a316c9b | 270 | |
80ff4f99 | 271 | /* |
490f2040 | 272 | * Commands additional to the ones defined in amcc-common.h |
80ff4f99 | 273 | */ |
ba2351f9 | 274 | #define CONFIG_CMD_DATE |
490f2040 SR |
275 | #define CONFIG_CMD_EXT2 |
276 | #define CONFIG_CMD_FAT | |
ba2351f9 | 277 | #define CONFIG_CMD_PCI |
ba2351f9 | 278 | #define CONFIG_CMD_SDRAM |
ba2351f9 | 279 | #define CONFIG_CMD_SNTP |
490f2040 | 280 | #define CONFIG_CMD_USB |
ba2351f9 | 281 | |
c57c7980 | 282 | #ifdef CONFIG_BAMBOO_NAND |
ba2351f9 JL |
283 | #define CONFIG_CMD_NAND |
284 | #endif | |
c57c7980 | 285 | |
3b6748ea SR |
286 | #define CONFIG_SUPPORT_VFAT |
287 | ||
490f2040 SR |
288 | /* Partitions */ |
289 | #define CONFIG_MAC_PARTITION | |
290 | #define CONFIG_DOS_PARTITION | |
291 | #define CONFIG_ISO_PARTITION | |
193dd958 | 292 | |
8a316c9b SR |
293 | /*----------------------------------------------------------------------- |
294 | * PCI stuff | |
295 | *----------------------------------------------------------------------- | |
296 | */ | |
297 | /* General PCI */ | |
c57c7980 SR |
298 | #define CONFIG_PCI /* include pci support */ |
299 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ | |
17f50f22 | 300 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
c57c7980 | 301 | #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ |
8a316c9b SR |
302 | |
303 | /* Board-specific PCI */ | |
8a316c9b SR |
304 | #define CFG_PCI_TARGET_INIT |
305 | #define CFG_PCI_MASTER_INIT | |
306 | ||
c57c7980 SR |
307 | #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
308 | #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
8a316c9b | 309 | |
8a316c9b | 310 | #endif /* __CONFIG_H */ |