]>
Commit | Line | Data |
---|---|---|
8a316c9b | 1 | /* |
8b39501d | 2 | * (C) Copyright 2005-2007 |
8a316c9b SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
8a316c9b SR |
6 | */ |
7 | ||
8 | /************************************************************************ | |
9 | * bamboo.h - configuration for BAMBOO board | |
10 | ***********************************************************************/ | |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /*----------------------------------------------------------------------- | |
15 | * High Level Configuration Options | |
16 | *----------------------------------------------------------------------*/ | |
17f50f22 | 17 | #define CONFIG_BAMBOO 1 /* Board is BAMBOO */ |
846b0dd2 | 18 | #define CONFIG_440EP 1 /* Specific PPC440EP support */ |
efa35cf1 | 19 | #define CONFIG_440 1 /* ... PPC440 family */ |
17f50f22 | 20 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
8a316c9b SR |
21 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
22 | ||
2ae18241 WD |
23 | #ifndef CONFIG_SYS_TEXT_BASE |
24 | #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 | |
25 | #endif | |
26 | ||
490f2040 SR |
27 | /* |
28 | * Include common defines/options for all AMCC eval boards | |
29 | */ | |
30 | #define CONFIG_HOSTNAME bamboo | |
31 | #include "amcc-common.h" | |
32 | ||
c57c7980 SR |
33 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
34 | ||
35 | /* | |
36 | * Please note that, if NAND support is enabled, the 2nd ethernet port | |
37 | * can't be used because of pin multiplexing. So, if you want to use the | |
38 | * 2nd ethernet port you have to "undef" the following define. | |
39 | */ | |
40 | #define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */ | |
41 | ||
8a316c9b SR |
42 | /*----------------------------------------------------------------------- |
43 | * Base addresses -- Note these are effective addresses where the | |
44 | * actual resources get mapped (not physical addresses) | |
45 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
46 | #define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */ |
47 | #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ | |
48 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 | |
49 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 | |
50 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 | |
8a316c9b SR |
51 | |
52 | /*Don't change either of these*/ | |
550650dd | 53 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ |
8a316c9b SR |
54 | /*Don't change either of these*/ |
55 | ||
6d0f6bcf JCPV |
56 | #define CONFIG_SYS_USB_DEVICE 0x50000000 |
57 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000 | |
58 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 | |
59 | #define CONFIG_SYS_NAND_ADDR 0x90000000 | |
60 | #define CONFIG_SYS_NAND2_ADDR 0x94000000 | |
8a316c9b SR |
61 | |
62 | /*----------------------------------------------------------------------- | |
63 | * Initial RAM & stack pointer (placed in SDRAM) | |
64 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
65 | #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
66 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ | |
553f0982 | 67 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
25ddd1fb | 68 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 69 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
8a316c9b | 70 | |
8a316c9b SR |
71 | /*----------------------------------------------------------------------- |
72 | * Serial Port | |
73 | *----------------------------------------------------------------------*/ | |
550650dd | 74 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
6d0f6bcf | 75 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ |
8a316c9b | 76 | |
8a316c9b SR |
77 | /*----------------------------------------------------------------------- |
78 | * NVRAM/RTC | |
79 | * | |
80 | * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF | |
81 | * The DS1558 code assumes this condition | |
82 | * | |
83 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 84 | #define CONFIG_SYS_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ |
17f50f22 SR |
85 | #define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ |
86 | ||
87 | /*----------------------------------------------------------------------- | |
88 | * Environment | |
89 | *----------------------------------------------------------------------*/ | |
cf959c7d | 90 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
5a1aceb0 | 91 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
17f50f22 | 92 | #else |
51bfee19 | 93 | #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ |
0e8d1586 | 94 | #define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ |
17f50f22 | 95 | #endif |
8a316c9b SR |
96 | |
97 | /*----------------------------------------------------------------------- | |
98 | * FLASH related | |
99 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */ |
101 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ | |
8a316c9b | 102 | |
6d0f6bcf JCPV |
103 | #undef CONFIG_SYS_FLASH_CHECKSUM |
104 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
105 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
8a316c9b | 106 | |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_FLASH_ADDR0 0x555 |
108 | #define CONFIG_SYS_FLASH_ADDR1 0x2aa | |
109 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char | |
8a316c9b | 110 | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ |
112 | #define CONFIG_SYS_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ | |
8a316c9b | 113 | |
5a1aceb0 | 114 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 115 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
6d0f6bcf | 116 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 117 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
17f50f22 | 118 | |
17f50f22 | 119 | /* Address and size of Redundant Environment Sector */ |
0e8d1586 JCPV |
120 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
121 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5a1aceb0 | 122 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
8a316c9b | 123 | |
cf959c7d SR |
124 | /* |
125 | * IPL (Initial Program Loader, integrated inside CPU) | |
126 | * Will load first 4k from NAND (SPL) into cache and execute it from there. | |
127 | * | |
128 | * SPL (Secondary Program Loader) | |
129 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL | |
130 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM | |
131 | * controller and the NAND controller so that the special U-Boot image can be | |
132 | * loaded from NAND to SDRAM. | |
133 | * | |
134 | * NUB (NAND U-Boot) | |
135 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started | |
136 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. | |
137 | * | |
138 | * On 440EPx the SPL is copied to SDRAM before the NAND controller is | |
139 | * set up. While still running from cache, I experienced problems accessing | |
140 | * the NAND controller. sr - 2006-08-25 | |
141 | */ | |
6d0f6bcf JCPV |
142 | #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ |
143 | #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ | |
144 | #define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */ | |
145 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ | |
146 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ | |
147 | #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) | |
cf959c7d SR |
148 | |
149 | /* | |
150 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) | |
151 | */ | |
6d0f6bcf JCPV |
152 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ |
153 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ | |
cf959c7d SR |
154 | |
155 | /* | |
156 | * Now the NAND chip has to be defined (no autodetection used!) | |
157 | */ | |
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ |
159 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
160 | #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ | |
161 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ | |
162 | #define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */ | |
163 | ||
164 | #define CONFIG_SYS_NAND_ECCSIZE 256 | |
165 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
6d0f6bcf | 166 | #define CONFIG_SYS_NAND_OOBSIZE 16 |
6d0f6bcf | 167 | #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} |
cf959c7d | 168 | |
51bfee19 | 169 | #ifdef CONFIG_ENV_IS_IN_NAND |
cf959c7d SR |
170 | /* |
171 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
172 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. | |
173 | */ | |
6d0f6bcf JCPV |
174 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
175 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) | |
0e8d1586 | 176 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
cf959c7d SR |
177 | #endif |
178 | ||
c57c7980 | 179 | /*----------------------------------------------------------------------- |
8b39501d | 180 | * NAND FLASH |
c57c7980 | 181 | *----------------------------------------------------------------------*/ |
6d0f6bcf | 182 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 |
6d0f6bcf JCPV |
183 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) |
184 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 } | |
185 | #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ | |
c57c7980 | 186 | |
cf959c7d | 187 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
6d0f6bcf | 188 | #define CONFIG_SYS_NAND_CS 1 |
cf959c7d | 189 | #else |
6d0f6bcf | 190 | #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ |
cf959c7d | 191 | /* Memory Bank 0 (NAND-FLASH) initialization */ |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_EBC_PB0AP 0x018003c0 |
193 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000) | |
cf959c7d SR |
194 | #endif |
195 | ||
8a316c9b SR |
196 | /*----------------------------------------------------------------------- |
197 | * DDR SDRAM | |
17f50f22 SR |
198 | *----------------------------------------------------------------------------- */ |
199 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ | |
fd49bf02 | 200 | #undef CONFIG_DDR_ECC /* don't use ECC */ |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */ |
202 | #define SPD_EEPROM_ADDRESS {CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51} | |
203 | #define CONFIG_SYS_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */ | |
d2f68006 | 204 | #define CONFIG_PROG_SDRAM_TLB |
8a316c9b SR |
205 | |
206 | /*----------------------------------------------------------------------- | |
207 | * I2C | |
208 | *----------------------------------------------------------------------*/ | |
880540de | 209 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
8a316c9b | 210 | |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
212 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) | |
213 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
214 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
215 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
8a316c9b | 216 | |
bb1f8b4f | 217 | #ifdef CONFIG_ENV_IS_IN_EEPROM |
0e8d1586 JCPV |
218 | #define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */ |
219 | #define CONFIG_ENV_OFFSET 0x0 | |
bb1f8b4f | 220 | #endif /* CONFIG_ENV_IS_IN_EEPROM */ |
17f50f22 | 221 | |
490f2040 SR |
222 | /* |
223 | * Default environment variables | |
224 | */ | |
17f50f22 | 225 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
490f2040 SR |
226 | CONFIG_AMCC_DEF_ENV \ |
227 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
228 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
229 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
230 | CONFIG_AMCC_DEF_ENV_NAND_UPD \ | |
17f50f22 SR |
231 | "kernel_addr=fff00000\0" \ |
232 | "ramdisk_addr=fff10000\0" \ | |
17f50f22 | 233 | "" |
8a316c9b | 234 | |
a00eccfe | 235 | #define CONFIG_HAS_ETH0 |
17f50f22 | 236 | #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ |
d6c61aab | 237 | #define CONFIG_PHY1_ADDR 1 |
c57c7980 SR |
238 | |
239 | #ifndef CONFIG_BAMBOO_NAND | |
8a316c9b | 240 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
c57c7980 SR |
241 | #endif /* CONFIG_BAMBOO_NAND */ |
242 | ||
846b0dd2 | 243 | #ifdef CONFIG_440EP |
8a316c9b SR |
244 | /* USB */ |
245 | #define CONFIG_USB_OHCI | |
246 | #define CONFIG_USB_STORAGE | |
247 | ||
248 | /*Comment this out to enable USB 1.1 device*/ | |
249 | #define USB_2_0_DEVICE | |
846b0dd2 | 250 | #endif /*CONFIG_440EP*/ |
8a316c9b | 251 | |
80ff4f99 | 252 | /* |
490f2040 | 253 | * Commands additional to the ones defined in amcc-common.h |
80ff4f99 | 254 | */ |
ba2351f9 | 255 | #define CONFIG_CMD_DATE |
490f2040 SR |
256 | #define CONFIG_CMD_EXT2 |
257 | #define CONFIG_CMD_FAT | |
ba2351f9 | 258 | #define CONFIG_CMD_PCI |
ba2351f9 | 259 | #define CONFIG_CMD_SDRAM |
ba2351f9 | 260 | #define CONFIG_CMD_SNTP |
490f2040 | 261 | #define CONFIG_CMD_USB |
ba2351f9 | 262 | |
c57c7980 | 263 | #ifdef CONFIG_BAMBOO_NAND |
ba2351f9 JL |
264 | #define CONFIG_CMD_NAND |
265 | #endif | |
c57c7980 | 266 | |
3b6748ea SR |
267 | #define CONFIG_SUPPORT_VFAT |
268 | ||
490f2040 SR |
269 | /* Partitions */ |
270 | #define CONFIG_MAC_PARTITION | |
271 | #define CONFIG_DOS_PARTITION | |
272 | #define CONFIG_ISO_PARTITION | |
193dd958 | 273 | |
8a316c9b SR |
274 | /*----------------------------------------------------------------------- |
275 | * PCI stuff | |
276 | *----------------------------------------------------------------------- | |
277 | */ | |
278 | /* General PCI */ | |
c57c7980 | 279 | #define CONFIG_PCI /* include pci support */ |
842033e6 | 280 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
c57c7980 | 281 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
17f50f22 | 282 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 283 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/ |
8a316c9b SR |
284 | |
285 | /* Board-specific PCI */ | |
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_PCI_TARGET_INIT |
287 | #define CONFIG_SYS_PCI_MASTER_INIT | |
8a316c9b | 288 | |
6d0f6bcf JCPV |
289 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
290 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
8a316c9b | 291 | |
8a316c9b | 292 | #endif /* __CONFIG_H */ |