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1 | /******************************************************************** |
2 | * | |
3 | * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms | |
4 | * | |
5 | * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/include/configs/barco.h,v $ | |
6 | * $Revision: 1.2 $ | |
7 | * $Author: mleeman $ | |
8 | * $Date: 2005/02/21 12:48:58 $ | |
9 | * | |
10 | * Last ChangeLog Entry | |
11 | * $Log: barco.h,v $ | |
12 | * Revision 1.2 2005/02/21 12:48:58 mleeman | |
13 | * update of copyright years (feedback wd) | |
14 | * | |
15 | * Revision 1.1 2005/02/14 09:29:25 mleeman | |
16 | * moved barcohydra.h to barco.h | |
17 | * | |
18 | * Revision 1.4 2005/02/09 12:56:23 mleeman | |
19 | * add generic header to track changes in sources | |
20 | * | |
21 | * | |
22 | *******************************************************************/ | |
23 | ||
24 | /* | |
25 | * (C) Copyright 2001, 2002 | |
26 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
27 | * | |
28 | * See file CREDITS for list of people who contributed to this | |
29 | * project. | |
30 | * | |
31 | * This program is free software; you can redistribute it and/or | |
32 | * modify it under the terms of the GNU General Public License as | |
33 | * published by the Free Software Foundation; either version 2 of | |
34 | * the License, or (at your option) any later version. | |
35 | * | |
36 | * This program is distributed in the hope that it will be useful, | |
37 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
38 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
39 | * GNU General Public License for more details. | |
40 | * | |
41 | * You should have received a copy of the GNU General Public License | |
42 | * along with this program; if not, write to the Free Software | |
43 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
44 | * MA 02111-1307 USA | |
45 | */ | |
46 | ||
47 | /* ------------------------------------------------------------------------- */ | |
48 | ||
49 | /* | |
50 | * board/config.h - configuration options, board specific | |
51 | */ | |
52 | ||
53 | #ifndef __CONFIG_H | |
54 | #define __CONFIG_H | |
55 | ||
56 | /* | |
57 | * High Level Configuration Options | |
58 | * (easy to change) | |
59 | */ | |
60 | ||
61 | #define CONFIG_MPC824X 1 | |
62 | #define CONFIG_MPC8245 1 | |
63 | #define CONFIG_BARCOBCD_STREAMING 1 | |
64 | ||
65 | #undef USE_DINK32 | |
66 | ||
67 | #define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */ | |
68 | #define CONFIG_BAUDRATE 9600 | |
69 | #define CONFIG_DRAM_SPEED 100 /* MHz */ | |
70 | ||
71 | #define CONFIG_BOOTARGS "mem=32M" | |
72 | ||
73 | /* Add support for a few extra bootp options like: | |
74 | * - File size | |
75 | * - DNS | |
76 | */ | |
77 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ | |
78 | CONFIG_BOOTP_BOOTFILESIZE | \ | |
79 | CONFIG_BOOTP_DNS) | |
80 | ||
81 | #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ | |
82 | CFG_CMD_ELF | \ | |
83 | CFG_CMD_I2C | \ | |
84 | CFG_CMD_EEPROM | \ | |
85 | CFG_CMD_PCI ) | |
86 | ||
87 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
88 | #include <cmd_confdefs.h> | |
89 | ||
90 | #define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */ | |
91 | #define CONFIG_BOOTDELAY 1 | |
92 | #define CONFIG_BOOTCOMMAND "boot_default" | |
93 | ||
94 | /* | |
95 | * Miscellaneous configurable options | |
96 | */ | |
97 | #define CFG_LONGHELP 1 /* undef to save memory */ | |
98 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
99 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
100 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
101 | #define CFG_MAXARGS 16 /* max number of command args */ | |
102 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
103 | #define CFG_LOAD_ADDR 0x00100000 /* default load address */ | |
104 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
105 | ||
106 | ||
107 | /*----------------------------------------------------------------------- | |
108 | * PCI stuff | |
109 | *----------------------------------------------------------------------- | |
110 | */ | |
111 | #define CONFIG_PCI /* include pci support */ | |
112 | #undef CONFIG_PCI_PNP | |
113 | #undef CFG_CMD_NET | |
114 | ||
115 | #define PCI_ENET0_IOADDR 0x80000000 | |
116 | #define PCI_ENET0_MEMADDR 0x80000000 | |
117 | #define PCI_ENET1_IOADDR 0x81000000 | |
118 | #define PCI_ENET1_MEMADDR 0x81000000 | |
119 | ||
120 | ||
121 | /*----------------------------------------------------------------------- | |
122 | * Start addresses for the final memory configuration | |
123 | * (Set up by the startup code) | |
124 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
125 | */ | |
126 | #define CFG_SDRAM_BASE 0x00000000 | |
127 | #define CFG_MAX_RAM_SIZE 0x02000000 | |
128 | ||
129 | #define CONFIG_LOGBUFFER | |
130 | #ifdef CONFIG_LOGBUFFER | |
131 | #define CFG_STDOUT_ADDR 0x1FFC000 | |
132 | #else | |
133 | #define CFG_STDOUT_ADDR 0x2B9000 | |
134 | #endif | |
135 | ||
136 | #define CFG_RESET_ADDRESS 0xFFF00100 | |
137 | ||
138 | #if defined (USE_DINK32) | |
139 | #define CFG_MONITOR_LEN 0x00030000 | |
140 | #define CFG_MONITOR_BASE 0x00090000 | |
141 | #define CFG_RAMBOOT 1 | |
142 | #define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) | |
143 | #define CFG_INIT_RAM_END 0x10000 | |
144 | #define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ | |
145 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
146 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
147 | #else | |
148 | #undef CFG_RAMBOOT | |
149 | #define CFG_MONITOR_LEN 0x00030000 | |
150 | #define CFG_MONITOR_BASE TEXT_BASE | |
151 | ||
152 | #define CFG_GBL_DATA_SIZE 128 | |
153 | ||
154 | #define CFG_INIT_RAM_ADDR 0x40000000 | |
155 | #define CFG_INIT_RAM_END 0x1000 | |
156 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
157 | ||
158 | #endif | |
159 | ||
160 | #define CFG_FLASH_BASE 0xFFF00000 | |
161 | #define CFG_FLASH_SIZE (8 * 1024 * 1024) /* Unity has onboard 1MByte flash */ | |
162 | #define CFG_ENV_IS_IN_FLASH 1 | |
163 | #define CFG_ENV_OFFSET 0x000047A4 /* Offset of Environment Sector */ | |
164 | #define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ | |
f57f70aa | 165 | /* #define ENV_CRC 0x8BF6F24B XXX - FIXME: gets defined automatically */ |
8e6f1a8e WD |
166 | |
167 | #define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ | |
168 | ||
169 | #define CFG_MEMTEST_START 0x00000000 /* memtest works on */ | |
170 | #define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */ | |
171 | ||
172 | #define CFG_EUMB_ADDR 0xFDF00000 | |
173 | ||
174 | #define CFG_FLASH_RANGE_BASE 0xFFC00000 /* flash memory address range */ | |
175 | #define CFG_FLASH_RANGE_SIZE 0x00400000 | |
176 | #define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */ | |
177 | #define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */ | |
178 | ||
179 | /* | |
180 | * select i2c support configuration | |
181 | * | |
182 | * Supported configurations are {none, software, hardware} drivers. | |
183 | * If the software driver is chosen, there are some additional | |
184 | * configuration items that the driver uses to drive the port pins. | |
185 | */ | |
186 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ | |
187 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
188 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
189 | #define CFG_I2C_SLAVE 0x7F | |
190 | ||
191 | #ifdef CONFIG_SOFT_I2C | |
192 | #error "Soft I2C is not configured properly. Please review!" | |
193 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
194 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
195 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
196 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
197 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
198 | else iop->pdat &= ~0x00010000 | |
199 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
200 | else iop->pdat &= ~0x00020000 | |
201 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
202 | #endif /* CONFIG_SOFT_I2C */ | |
203 | ||
204 | #define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */ | |
205 | #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
206 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 | |
207 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
208 | ||
209 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
210 | #define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM } | |
211 | #define CFG_DBUS_SIZE2 1 | |
212 | ||
213 | /*----------------------------------------------------------------------- | |
214 | * Definitions for initial stack pointer and data area (in DPRAM) | |
215 | */ | |
216 | ||
217 | ||
218 | /* | |
219 | * NS16550 Configuration (internal DUART) | |
220 | */ | |
221 | /* | |
222 | * Low Level Configuration Settings | |
223 | * (address mappings, register initial values, etc.) | |
224 | * You should know what you are doing if you make changes here. | |
225 | */ | |
226 | ||
227 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
228 | ||
229 | #define CFG_ROMNAL 0x0F /*rom/flash next access time */ | |
230 | #define CFG_ROMFAL 0x1E /*rom/flash access time */ | |
231 | ||
232 | #define CFG_REFINT 0x8F /* no of clock cycles between CBR refresh cycles */ | |
233 | ||
234 | /* the following are for SDRAM only*/ | |
235 | #define CFG_BSTOPRE 0x25C /* Burst To Precharge, sets open page interval */ | |
236 | #define CFG_REFREC 8 /* Refresh to activate interval */ | |
237 | #define CFG_RDLAT 4 /* data latency from read command */ | |
238 | #define CFG_PRETOACT 3 /* Precharge to activate interval */ | |
239 | #define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ | |
240 | #define CFG_ACTORW 2 /* Activate to R/W */ | |
241 | #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */ | |
242 | #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ | |
243 | ||
244 | #define CFG_REGISTERD_TYPE_BUFFER 1 | |
245 | #define CFG_EXTROM 0 | |
246 | #define CFG_REGDIMM 0 | |
247 | ||
248 | ||
249 | /* memory bank settings*/ | |
250 | /* | |
251 | * only bits 20-29 are actually used from these vales to set the | |
252 | * start/end address the upper two bits will be 0, and the lower 20 | |
253 | * bits will be set to 0x00000 for a start address, or 0xfffff for an | |
254 | * end address | |
255 | */ | |
256 | #define CFG_BANK0_START 0x00000000 | |
257 | #define CFG_BANK0_END 0x01FFFFFF | |
258 | #define CFG_BANK0_ENABLE 1 | |
259 | #define CFG_BANK1_START 0x02000000 | |
260 | #define CFG_BANK1_END 0x02ffffff | |
261 | #define CFG_BANK1_ENABLE 0 | |
262 | #define CFG_BANK2_START 0x03f00000 | |
263 | #define CFG_BANK2_END 0x03ffffff | |
264 | #define CFG_BANK2_ENABLE 0 | |
265 | #define CFG_BANK3_START 0x04000000 | |
266 | #define CFG_BANK3_END 0x04ffffff | |
267 | #define CFG_BANK3_ENABLE 0 | |
268 | #define CFG_BANK4_START 0x05000000 | |
269 | #define CFG_BANK4_END 0x05FFFFFF | |
270 | #define CFG_BANK4_ENABLE 0 | |
271 | #define CFG_BANK5_START 0x06000000 | |
272 | #define CFG_BANK5_END 0x06FFFFFF | |
273 | #define CFG_BANK5_ENABLE 0 | |
274 | #define CFG_BANK6_START 0x07000000 | |
275 | #define CFG_BANK6_END 0x07FFFFFF | |
276 | #define CFG_BANK6_ENABLE 0 | |
277 | #define CFG_BANK7_START 0x08000000 | |
278 | #define CFG_BANK7_END 0x08FFFFFF | |
279 | #define CFG_BANK7_ENABLE 0 | |
280 | /* | |
281 | * Memory bank enable bitmask, specifying which of the banks defined above | |
282 | are actually present. MSB is for bank #7, LSB is for bank #0. | |
283 | */ | |
284 | #define CFG_BANK_ENABLE 0x01 | |
285 | ||
286 | #define CFG_ODCR 0xff /* configures line driver impedances, */ | |
287 | /* see 8240 book for bit definitions */ | |
288 | #define CFG_PGMAX 0x32 /* how long the 8240 retains the */ | |
289 | /* currently accessed page in memory */ | |
290 | /* see 8240 book for details */ | |
291 | ||
292 | /* SDRAM 0 - 256MB */ | |
293 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
294 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
295 | ||
296 | /* stack in DCACHE @ 1GB (no backing mem) */ | |
297 | #if defined(USE_DINK32) | |
298 | #define CFG_IBAT1L (0x40000000 | BATL_PP_00 ) | |
299 | #define CFG_IBAT1U (0x40000000 | BATU_BL_128K ) | |
300 | #else | |
301 | #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) | |
302 | #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
303 | #endif | |
304 | ||
305 | /* PCI memory */ | |
306 | #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) | |
307 | #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
308 | ||
309 | /* Flash, config addrs, etc */ | |
310 | #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) | |
311 | #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
312 | ||
313 | #define CFG_DBAT0L CFG_IBAT0L | |
314 | #define CFG_DBAT0U CFG_IBAT0U | |
315 | #define CFG_DBAT1L CFG_IBAT1L | |
316 | #define CFG_DBAT1U CFG_IBAT1U | |
317 | #define CFG_DBAT2L CFG_IBAT2L | |
318 | #define CFG_DBAT2U CFG_IBAT2U | |
319 | #define CFG_DBAT3L CFG_IBAT3L | |
320 | #define CFG_DBAT3U CFG_IBAT3U | |
321 | ||
322 | /* | |
323 | * For booting Linux, the board info and command line data | |
324 | * have to be in the first 8 MB of memory, since this is | |
325 | * the maximum mapped by the Linux kernel during initialization. | |
326 | */ | |
327 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
328 | /*----------------------------------------------------------------------- | |
329 | * FLASH organization | |
330 | */ | |
331 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
332 | #define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */ | |
333 | ||
334 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
335 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
336 | ||
337 | #define CFG_FLASH_CHECKSUM | |
338 | ||
339 | /*----------------------------------------------------------------------- | |
340 | * Cache Configuration | |
341 | */ | |
342 | #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ | |
343 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
344 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
345 | #endif | |
346 | ||
347 | ||
348 | /* | |
349 | * Internal Definitions | |
350 | * | |
351 | * Boot Flags | |
352 | */ | |
353 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
354 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
355 | ||
356 | /* values according to the manual */ | |
357 | ||
358 | #define CONFIG_DRAM_50MHZ 1 | |
359 | #define CONFIG_SDRAM_50MHZ | |
360 | ||
361 | #define CONFIG_DISK_SPINUP_TIME 1000000 | |
362 | ||
363 | ||
364 | #endif /* __CONFIG_H */ |