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Commit | Line | Data |
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37aac2d3 | 1 | /* |
a187559e | 2 | * U-Boot - Configuration file for BF527 AD7160-EVAL board |
37aac2d3 MH |
3 | */ |
4 | ||
5 | #ifndef __CONFIG_BF527_AD7160_EVAL_H__ | |
6 | #define __CONFIG_BF527_AD7160_EVAL_H__ | |
7 | ||
8 | #include <asm/config-pre.h> | |
9 | ||
37aac2d3 MH |
10 | /* |
11 | * Processor Settings | |
12 | */ | |
fbcf8e8c | 13 | #define CONFIG_BFIN_CPU bf527-0.2 |
37aac2d3 MH |
14 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER |
15 | ||
37aac2d3 MH |
16 | /* |
17 | * Clock Settings | |
18 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV | |
19 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV | |
20 | */ | |
21 | /* CONFIG_CLKIN_HZ is any value in Hz */ | |
22 | #define CONFIG_CLKIN_HZ 24000000 | |
23 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ | |
24 | /* 1 = CLKIN / 2 */ | |
25 | #define CONFIG_CLKIN_HALF 0 | |
26 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ | |
27 | /* 1 = bypass PLL */ | |
28 | #define CONFIG_PLL_BYPASS 0 | |
29 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ | |
30 | /* Values can range from 0-63 (where 0 means 64) */ | |
31 | #define CONFIG_VCO_MULT 25 | |
32 | /* CCLK_DIV controls the core clock divider */ | |
33 | /* Values can be 1, 2, 4, or 8 ONLY */ | |
34 | #define CONFIG_CCLK_DIV 1 | |
35 | /* SCLK_DIV controls the system clock divider */ | |
36 | /* Values can range from 1-15 */ | |
37 | #define CONFIG_SCLK_DIV 5 | |
38 | ||
37aac2d3 MH |
39 | /* |
40 | * Memory Settings | |
41 | */ | |
42 | #define CONFIG_MEM_ADD_WDTH 10 | |
43 | #define CONFIG_MEM_SIZE 64 | |
44 | ||
45 | #define CONFIG_EBIU_SDRRC_VAL 0x03F6 | |
46 | #define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) | |
47 | ||
48 | #define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) | |
49 | #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) | |
50 | #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) | |
51 | ||
52 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) | |
53 | #define CONFIG_SYS_MALLOC_LEN (640 * 1024) | |
54 | ||
37aac2d3 MH |
55 | /* |
56 | * NAND Settings | |
57 | * (can't be used same time as ethernet) | |
58 | */ | |
59 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) | |
60 | # define CONFIG_BFIN_NFC | |
61 | # define CONFIG_BFIN_NFC_BOOTROM_ECC | |
62 | #endif | |
63 | #ifdef CONFIG_BFIN_NFC | |
64 | #define CONFIG_BFIN_NFC_CTL_VAL 0x0033 | |
65 | #define CONFIG_DRIVER_NAND_BFIN | |
66 | #define CONFIG_SYS_NAND_BASE 0 /* not actually used */ | |
67 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
37aac2d3 MH |
68 | #endif |
69 | ||
37aac2d3 MH |
70 | /* |
71 | * Flash Settings | |
72 | */ | |
73 | #define CONFIG_FLASH_CFI_DRIVER | |
74 | #define CONFIG_SYS_FLASH_BASE 0x20000000 | |
75 | #define CONFIG_SYS_FLASH_CFI | |
76 | #define CONFIG_SYS_FLASH_PROTECTION | |
77 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
78 | #define CONFIG_SYS_MAX_FLASH_SECT 259 | |
79 | ||
37aac2d3 MH |
80 | /* |
81 | * SPI Settings | |
82 | */ | |
83 | #define CONFIG_BFIN_SPI | |
84 | #define CONFIG_ENV_SPI_MAX_HZ 30000000 | |
85 | #define CONFIG_SF_DEFAULT_SPEED 30000000 | |
37aac2d3 | 86 | |
37aac2d3 MH |
87 | /* |
88 | * Env Storage Settings | |
89 | */ | |
90 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) | |
91 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
92 | #define CONFIG_ENV_OFFSET 0x10000 | |
93 | #define CONFIG_ENV_SIZE 0x2000 | |
94 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
95 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR | |
96 | #elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) | |
97 | #define CONFIG_ENV_IS_IN_NAND | |
98 | #define CONFIG_ENV_OFFSET 0x40000 | |
99 | #define CONFIG_ENV_SIZE 0x20000 | |
100 | #else | |
101 | #define CONFIG_ENV_IS_IN_FLASH | |
102 | #define CONFIG_ENV_OFFSET 0x4000 | |
103 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) | |
104 | #define CONFIG_ENV_SIZE 0x2000 | |
105 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
106 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR | |
107 | #endif | |
108 | ||
37aac2d3 MH |
109 | /* |
110 | * I2C Settings | |
111 | */ | |
c469703b | 112 | #define CONFIG_SYS_I2C |
fea9b69a | 113 | #define CONFIG_SYS_I2C_ADI |
37aac2d3 | 114 | |
37aac2d3 MH |
115 | /* |
116 | * SPI_MMC Settings | |
117 | */ | |
118 | #define CONFIG_MMC | |
14dda9df MF |
119 | #define CONFIG_GENERIC_MMC |
120 | #define CONFIG_MMC_SPI | |
37aac2d3 | 121 | |
37aac2d3 MH |
122 | /* |
123 | * Misc Settings | |
124 | */ | |
125 | #define CONFIG_MISC_INIT_R | |
126 | #define CONFIG_UART_CONSOLE 0 | |
37aac2d3 MH |
127 | |
128 | /* | |
129 | * Pull in common ADI header for remaining command/environment setup | |
130 | */ | |
131 | #include <configs/bfin_adi_common.h> | |
132 | ||
133 | #endif |