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Commit | Line | Data |
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d9a5d113 MF |
1 | /* |
2 | * U-boot - Configuration file for BF537 STAMP board | |
3 | */ | |
4 | ||
5 | #ifndef __CONFIG_BF527_EZKIT_H__ | |
6 | #define __CONFIG_BF527_EZKIT_H__ | |
7 | ||
f348ab85 | 8 | #include <asm/config-pre.h> |
d9a5d113 MF |
9 | |
10 | ||
11 | /* | |
12 | * Processor Settings | |
13 | */ | |
fbcf8e8c | 14 | #define CONFIG_BFIN_CPU bf527-0.0 |
d9a5d113 MF |
15 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA |
16 | ||
17 | ||
18 | /* | |
19 | * Clock Settings | |
20 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV | |
21 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV | |
22 | */ | |
23 | /* CONFIG_CLKIN_HZ is any value in Hz */ | |
24 | #define CONFIG_CLKIN_HZ 25000000 | |
25 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ | |
26 | /* 1 = CLKIN / 2 */ | |
27 | #define CONFIG_CLKIN_HALF 0 | |
28 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ | |
29 | /* 1 = bypass PLL */ | |
30 | #define CONFIG_PLL_BYPASS 0 | |
31 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ | |
32 | /* Values can range from 0-63 (where 0 means 64) */ | |
33 | #define CONFIG_VCO_MULT 21 | |
34 | /* CCLK_DIV controls the core clock divider */ | |
35 | /* Values can be 1, 2, 4, or 8 ONLY */ | |
36 | #define CONFIG_CCLK_DIV 1 | |
37 | /* SCLK_DIV controls the system clock divider */ | |
38 | /* Values can range from 1-15 */ | |
39 | #define CONFIG_SCLK_DIV 4 | |
40 | ||
41 | ||
42 | /* | |
43 | * Memory Settings | |
44 | */ | |
45 | #define CONFIG_MEM_ADD_WDTH 10 | |
46 | #define CONFIG_MEM_SIZE 64 | |
47 | ||
48 | #define CONFIG_EBIU_SDRRC_VAL 0x03F6 | |
49 | #define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) | |
50 | ||
51 | #define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) | |
52 | #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) | |
53 | #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) | |
54 | ||
55 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) | |
56 | #define CONFIG_SYS_MALLOC_LEN (640 * 1024) | |
57 | ||
58 | ||
59 | /* | |
60 | * NAND Settings | |
61 | * (can't be used same time as ethernet) | |
62 | */ | |
63 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) | |
b7659ef2 MF |
64 | # define CONFIG_BFIN_NFC |
65 | # define CONFIG_BFIN_NFC_BOOTROM_ECC | |
d9a5d113 MF |
66 | #endif |
67 | #ifdef CONFIG_BFIN_NFC | |
68 | #define CONFIG_BFIN_NFC_CTL_VAL 0x0033 | |
69 | #define CONFIG_DRIVER_NAND_BFIN | |
70 | #define CONFIG_SYS_NAND_BASE 0 /* not actually used */ | |
71 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
d9a5d113 MF |
72 | #endif |
73 | ||
74 | ||
75 | /* | |
76 | * Network Settings | |
77 | */ | |
78 | #if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \ | |
79 | !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC) | |
80 | #define ADI_CMDS_NETWORK 1 | |
81 | #define CONFIG_BFIN_MAC | |
82 | #define CONFIG_RMII | |
83 | #define CONFIG_NETCONSOLE 1 | |
d9a5d113 MF |
84 | #endif |
85 | #define CONFIG_HOSTNAME bf527-ezkit | |
86 | /* Uncomment next line to use fixed MAC address */ | |
87 | /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ | |
c42f56d9 | 88 | #define CONFIG_LIB_RAND |
d9a5d113 MF |
89 | |
90 | /* | |
91 | * Flash Settings | |
92 | */ | |
93 | #define CONFIG_FLASH_CFI_DRIVER | |
94 | #define CONFIG_SYS_FLASH_BASE 0x20000000 | |
95 | #define CONFIG_SYS_FLASH_CFI | |
96 | #define CONFIG_SYS_FLASH_PROTECTION | |
97 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
98 | #define CONFIG_SYS_MAX_FLASH_SECT 259 | |
99 | ||
100 | ||
101 | /* | |
102 | * SPI Settings | |
103 | */ | |
104 | #define CONFIG_BFIN_SPI | |
105 | #define CONFIG_ENV_SPI_MAX_HZ 30000000 | |
afac8b07 | 106 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
d9a5d113 MF |
107 | #define CONFIG_SPI_FLASH |
108 | #define CONFIG_SPI_FLASH_STMICRO | |
109 | ||
110 | ||
111 | /* | |
112 | * Env Storage Settings | |
113 | */ | |
114 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) | |
115 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
53310b88 | 116 | #define CONFIG_ENV_OFFSET 0x10000 |
d9a5d113 | 117 | #define CONFIG_ENV_SIZE 0x2000 |
53310b88 | 118 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
b7659ef2 MF |
119 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR |
120 | #elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) | |
121 | #define CONFIG_ENV_IS_IN_NAND | |
122 | #define CONFIG_ENV_OFFSET 0x40000 | |
123 | #define CONFIG_ENV_SIZE 0x20000 | |
d9a5d113 MF |
124 | #else |
125 | #define CONFIG_ENV_IS_IN_FLASH | |
126 | #define CONFIG_ENV_OFFSET 0x4000 | |
127 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) | |
128 | #define CONFIG_ENV_SIZE 0x2000 | |
129 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
76d82187 | 130 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR |
b7659ef2 | 131 | #endif |
d9a5d113 MF |
132 | |
133 | ||
134 | /* | |
135 | * I2C Settings | |
136 | */ | |
c469703b | 137 | #define CONFIG_SYS_I2C |
fea9b69a | 138 | #define CONFIG_SYS_I2C_ADI |
d9a5d113 MF |
139 | |
140 | ||
141 | /* | |
142 | * USB Settings | |
143 | */ | |
144 | #if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) | |
145 | #define CONFIG_USB | |
146 | #define CONFIG_MUSB_HCD | |
147 | #define CONFIG_USB_BLACKFIN | |
148 | #define CONFIG_USB_STORAGE | |
149 | #define CONFIG_MUSB_TIMEOUT 100000 | |
150 | #endif | |
151 | ||
955020c6 SZ |
152 | /* Don't waste time transferring a logo over the UART */ |
153 | #if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) | |
154 | /*# define CONFIG_VIDEO*/ | |
155 | #endif | |
d9a5d113 | 156 | |
10eafa10 MH |
157 | /* |
158 | * Video Settings | |
159 | */ | |
955020c6 | 160 | #ifdef CONFIG_VIDEO |
d24f2d32 | 161 | #ifdef CONFIG_BF527_EZKIT_REV_2_1 |
10eafa10 MH |
162 | # define CONFIG_LQ035Q1_SPI_BUS 0 |
163 | # define CONFIG_LQ035Q1_SPI_CS 7 | |
42c6e9ad MF |
164 | # define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI |
165 | #else | |
166 | # define CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI | |
167 | #endif | |
168 | ||
169 | #ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI | |
170 | # define EASYLOGO_HEADER <asm/bfin_logo_rgb565_230x230_lzma.h> | |
171 | #else | |
172 | # define EASYLOGO_HEADER <asm/bfin_logo_230x230_lzma.h> | |
10eafa10 | 173 | #endif |
955020c6 | 174 | #endif /* CONFIG_VIDEO */ |
10eafa10 | 175 | |
d9a5d113 MF |
176 | /* |
177 | * Misc Settings | |
178 | */ | |
179 | #define CONFIG_MISC_INIT_R | |
180 | #define CONFIG_RTC_BFIN | |
181 | #define CONFIG_UART_CONSOLE 1 | |
d9a5d113 MF |
182 | |
183 | /* | |
184 | * Pull in common ADI header for remaining command/environment setup | |
185 | */ | |
186 | #include <configs/bfin_adi_common.h> | |
187 | ||
d9a5d113 | 188 | #endif |