]>
Commit | Line | Data |
---|---|---|
3f0606ad AL |
1 | /* |
2 | * U-boot - Configuration file for BF533 STAMP board | |
3 | */ | |
4 | ||
cf6f469e MF |
5 | #ifndef __CONFIG_BF533_STAMP_H__ |
6 | #define __CONFIG_BF533_STAMP_H__ | |
3f0606ad | 7 | |
f348ab85 | 8 | #include <asm/config-pre.h> |
f7ce12cb | 9 | |
3f0606ad | 10 | |
3f0606ad | 11 | /* |
cf6f469e | 12 | * Processor Settings |
3f0606ad | 13 | */ |
fbcf8e8c | 14 | #define CONFIG_BFIN_CPU bf533-0.3 |
cf6f469e | 15 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS |
3f0606ad | 16 | |
3f0606ad | 17 | /* |
cf6f469e MF |
18 | * Clock Settings |
19 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV | |
20 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV | |
3f0606ad | 21 | */ |
cf6f469e MF |
22 | /* CONFIG_CLKIN_HZ is any value in Hz */ |
23 | #define CONFIG_CLKIN_HZ 11059200 | |
24 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ | |
25 | /* 1 = CLKIN / 2 */ | |
26 | #define CONFIG_CLKIN_HALF 0 | |
27 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ | |
28 | /* 1 = bypass PLL */ | |
29 | #define CONFIG_PLL_BYPASS 0 | |
30 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ | |
31 | /* Values can range from 0-63 (where 0 means 64) */ | |
9f64ba24 | 32 | #define CONFIG_VCO_MULT 45 |
cf6f469e MF |
33 | /* CCLK_DIV controls the core clock divider */ |
34 | /* Values can be 1, 2, 4, or 8 ONLY */ | |
35 | #define CONFIG_CCLK_DIV 1 | |
36 | /* SCLK_DIV controls the system clock divider */ | |
37 | /* Values can range from 1-15 */ | |
baf35705 | 38 | #define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */ |
3f0606ad | 39 | |
3f0606ad | 40 | /* |
cf6f469e | 41 | * Memory Settings |
3f0606ad | 42 | */ |
cf6f469e MF |
43 | #define CONFIG_MEM_ADD_WDTH 11 |
44 | #define CONFIG_MEM_SIZE 128 | |
3f0606ad | 45 | |
cf6f469e MF |
46 | #define CONFIG_EBIU_SDRRC_VAL 0x268 |
47 | #define CONFIG_EBIU_SDGCTL_VAL 0x911109 | |
3f0606ad | 48 | |
cf6f469e MF |
49 | #define CONFIG_EBIU_AMGCTL_VAL 0xFF |
50 | #define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3 | |
51 | #define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983 | |
3f0606ad | 52 | |
cf6f469e MF |
53 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
54 | #define CONFIG_SYS_MALLOC_LEN (384 * 1024) | |
3f0606ad | 55 | |
3f0606ad AL |
56 | |
57 | /* | |
cf6f469e | 58 | * Network Settings |
3f0606ad | 59 | */ |
cf6f469e | 60 | #define ADI_CMDS_NETWORK 1 |
7194ab80 | 61 | #define CONFIG_SMC91111 1 |
cf6f469e MF |
62 | #define CONFIG_SMC91111_BASE 0x20300300 |
63 | #define SMC91111_EEPROM_INIT() \ | |
64 | do { \ | |
7194ab80 BW |
65 | bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \ |
66 | bfin_write_FIO_FLAG_C(PF1); \ | |
67 | bfin_write_FIO_FLAG_S(PF0); \ | |
cf6f469e MF |
68 | SSYNC(); \ |
69 | } while (0) | |
70 | #define CONFIG_HOSTNAME bf533-stamp | |
3f0606ad | 71 | |
3f0606ad | 72 | |
ea818dbb HS |
73 | /* I2C */ |
74 | #define CONFIG_SYS_I2C | |
75 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
76 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
77 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0 | |
78 | /* | |
79 | * Software (bit-bang) I2C driver configuration | |
80 | */ | |
e5cb60a0 SZ |
81 | #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3 |
82 | #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2 | |
ea818dbb | 83 | |
3f0606ad | 84 | /* |
cf6f469e | 85 | * Flash Settings |
3f0606ad | 86 | */ |
cf6f469e MF |
87 | #define CONFIG_FLASH_CFI_DRIVER |
88 | #define CONFIG_SYS_FLASH_BASE 0x20000000 | |
89 | #define CONFIG_SYS_FLASH_CFI | |
90 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET | |
91 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
92 | #define CONFIG_SYS_MAX_FLASH_SECT 67 | |
3f0606ad | 93 | |
079a136c | 94 | /* |
cf6f469e | 95 | * SPI Settings |
079a136c | 96 | */ |
cf6f469e MF |
97 | #define CONFIG_BFIN_SPI |
98 | #define CONFIG_ENV_SPI_MAX_HZ 30000000 | |
c49eabef | 99 | /* |
afac8b07 | 100 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
f453220c | 101 | #define CONFIG_SPI_FLASH_ALL |
c49eabef | 102 | */ |
079a136c | 103 | |
ba2351f9 | 104 | /* |
cf6f469e | 105 | * Env Storage Settings |
ba2351f9 | 106 | */ |
cf6f469e MF |
107 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
108 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
bc43a8d8 | 109 | #define CONFIG_ENV_OFFSET 0x10000 |
cf6f469e | 110 | #define CONFIG_ENV_SIZE 0x2000 |
bc43a8d8 | 111 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
cf6f469e MF |
112 | #else |
113 | #define CONFIG_ENV_IS_IN_FLASH | |
114 | #define CONFIG_ENV_OFFSET 0x4000 | |
115 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) | |
116 | #define CONFIG_ENV_SIZE 0x2000 | |
117 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
ba2351f9 | 118 | #endif |
cf6f469e MF |
119 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) |
120 | #define ENV_IS_EMBEDDED | |
3f0606ad | 121 | #else |
76d82187 | 122 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR |
3f0606ad | 123 | #endif |
9ff67e5e MF |
124 | #ifdef ENV_IS_EMBEDDED |
125 | /* WARNING - the following is hand-optimized to fit within | |
126 | * the sector before the environment sector. If it throws | |
127 | * an error during compilation remove an object here to get | |
128 | * it linked after the configuration sector. | |
129 | */ | |
130 | # define LDS_BOARD_TEXT \ | |
e2906a59 MY |
131 | arch/blackfin/lib/built-in.o (.text*); \ |
132 | arch/blackfin/cpu/built-in.o (.text*); \ | |
9ff67e5e | 133 | . = DEFINED(env_offset) ? env_offset : .; \ |
c70e7ddb | 134 | common/env_embedded.o (.text*); |
9ff67e5e | 135 | #endif |
3f0606ad | 136 | |
3f0606ad AL |
137 | |
138 | /* | |
cf6f469e | 139 | * I2C Settings |
3f0606ad | 140 | */ |
ea818dbb HS |
141 | #define CONFIG_SYS_I2C_SOFT |
142 | #ifdef CONFIG_SYS_I2C_SOFT | |
143 | #define CONFIG_SYS_I2C | |
beb60e77 MF |
144 | #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3 |
145 | #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2 | |
ea818dbb HS |
146 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
147 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
148 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0 | |
149 | #endif | |
3f0606ad AL |
150 | |
151 | /* | |
cf6f469e | 152 | * Compact Flash / IDE / ATA Settings |
3f0606ad AL |
153 | */ |
154 | ||
155 | /* Enabled below option for CF support */ | |
cf6f469e MF |
156 | /* #define CONFIG_STAMP_CF */ |
157 | #if defined(CONFIG_STAMP_CF) | |
158 | #define CONFIG_MISC_INIT_R | |
8db13d63 | 159 | #define CONFIG_DOS_PARTITION 1 |
8db13d63 AL |
160 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
161 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
162 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ | |
3f0606ad | 163 | |
cf6f469e MF |
164 | #define CONFIG_SYS_IDE_MAXBUS 1 |
165 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1) | |
3f0606ad | 166 | |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_ATA_BASE_ADDR 0x20200000 |
168 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
3f0606ad | 169 | |
cf6f469e MF |
170 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ |
171 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ | |
172 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */ | |
3f0606ad | 173 | |
6d0f6bcf | 174 | #define CONFIG_SYS_ATA_STRIDE 2 |
cf6f469e MF |
175 | |
176 | #undef CONFIG_EBIU_AMBCTL1_VAL | |
177 | #define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2 | |
3f0606ad AL |
178 | #endif |
179 | ||
cf6f469e | 180 | |
3f0606ad | 181 | /* |
cf6f469e | 182 | * Misc Settings |
3f0606ad | 183 | */ |
cf6f469e MF |
184 | #define CONFIG_RTC_BFIN |
185 | #define CONFIG_UART_CONSOLE 0 | |
3f0606ad | 186 | |
cf6f469e MF |
187 | /* FLASH/ETHERNET uses the same async bank */ |
188 | #define SHARED_RESOURCES 1 | |
3f0606ad | 189 | |
23fd959e MF |
190 | /* define to enable boot progress via leds */ |
191 | /* #define CONFIG_SHOW_BOOT_PROGRESS */ | |
192 | ||
193 | /* define to enable run status via led */ | |
194 | /* #define CONFIG_STATUS_LED */ | |
195 | #ifdef CONFIG_STATUS_LED | |
a84774f5 | 196 | #define CONFIG_GPIO_LED |
23fd959e | 197 | #define CONFIG_BOARD_SPECIFIC_LED |
a84774f5 | 198 | /* use LED0 to indicate booting/alive */ |
23fd959e | 199 | #define STATUS_LED_BOOT 0 |
a84774f5 | 200 | #define STATUS_LED_BIT GPIO_PF2 |
23fd959e MF |
201 | #define STATUS_LED_STATE STATUS_LED_ON |
202 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4) | |
a84774f5 | 203 | /* use LED1 to indicate crash */ |
23fd959e | 204 | #define STATUS_LED_CRASH 1 |
a84774f5 | 205 | #define STATUS_LED_BIT1 GPIO_PF3 |
23fd959e MF |
206 | #define STATUS_LED_STATE1 STATUS_LED_ON |
207 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) | |
a84774f5 | 208 | /* #define STATUS_LED_BIT2 GPIO_PF4 */ |
23fd959e MF |
209 | #endif |
210 | ||
cf6f469e MF |
211 | /* define to enable splash screen support */ |
212 | /* #define CONFIG_VIDEO */ | |
3f0606ad | 213 | |
3f0606ad AL |
214 | |
215 | /* | |
cf6f469e | 216 | * Pull in common ADI header for remaining command/environment setup |
3f0606ad | 217 | */ |
cf6f469e | 218 | #include <configs/bfin_adi_common.h> |
9171fc81 | 219 | |
3f0606ad | 220 | #endif |