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Commit | Line | Data |
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3f0606ad AL |
1 | /* |
2 | * U-boot - Configuration file for BF533 STAMP board | |
3 | */ | |
4 | ||
cf6f469e MF |
5 | #ifndef __CONFIG_BF533_STAMP_H__ |
6 | #define __CONFIG_BF533_STAMP_H__ | |
3f0606ad | 7 | |
f348ab85 | 8 | #include <asm/config-pre.h> |
f7ce12cb | 9 | |
3f0606ad | 10 | |
3f0606ad | 11 | /* |
cf6f469e | 12 | * Processor Settings |
3f0606ad | 13 | */ |
fbcf8e8c | 14 | #define CONFIG_BFIN_CPU bf533-0.3 |
cf6f469e | 15 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS |
3f0606ad | 16 | |
3f0606ad | 17 | /* |
cf6f469e MF |
18 | * Clock Settings |
19 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV | |
20 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV | |
3f0606ad | 21 | */ |
cf6f469e MF |
22 | /* CONFIG_CLKIN_HZ is any value in Hz */ |
23 | #define CONFIG_CLKIN_HZ 11059200 | |
24 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ | |
25 | /* 1 = CLKIN / 2 */ | |
26 | #define CONFIG_CLKIN_HALF 0 | |
27 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ | |
28 | /* 1 = bypass PLL */ | |
29 | #define CONFIG_PLL_BYPASS 0 | |
30 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ | |
31 | /* Values can range from 0-63 (where 0 means 64) */ | |
9f64ba24 | 32 | #define CONFIG_VCO_MULT 45 |
cf6f469e MF |
33 | /* CCLK_DIV controls the core clock divider */ |
34 | /* Values can be 1, 2, 4, or 8 ONLY */ | |
35 | #define CONFIG_CCLK_DIV 1 | |
36 | /* SCLK_DIV controls the system clock divider */ | |
37 | /* Values can range from 1-15 */ | |
baf35705 | 38 | #define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */ |
3f0606ad | 39 | |
3f0606ad | 40 | /* |
cf6f469e | 41 | * Memory Settings |
3f0606ad | 42 | */ |
cf6f469e MF |
43 | #define CONFIG_MEM_ADD_WDTH 11 |
44 | #define CONFIG_MEM_SIZE 128 | |
3f0606ad | 45 | |
cf6f469e MF |
46 | #define CONFIG_EBIU_SDRRC_VAL 0x268 |
47 | #define CONFIG_EBIU_SDGCTL_VAL 0x911109 | |
3f0606ad | 48 | |
cf6f469e MF |
49 | #define CONFIG_EBIU_AMGCTL_VAL 0xFF |
50 | #define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3 | |
51 | #define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983 | |
3f0606ad | 52 | |
cf6f469e MF |
53 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
54 | #define CONFIG_SYS_MALLOC_LEN (384 * 1024) | |
3f0606ad | 55 | |
3f0606ad AL |
56 | |
57 | /* | |
cf6f469e | 58 | * Network Settings |
3f0606ad | 59 | */ |
cf6f469e | 60 | #define ADI_CMDS_NETWORK 1 |
7194ab80 | 61 | #define CONFIG_SMC91111 1 |
cf6f469e MF |
62 | #define CONFIG_SMC91111_BASE 0x20300300 |
63 | #define SMC91111_EEPROM_INIT() \ | |
64 | do { \ | |
7194ab80 BW |
65 | bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \ |
66 | bfin_write_FIO_FLAG_C(PF1); \ | |
67 | bfin_write_FIO_FLAG_S(PF0); \ | |
cf6f469e MF |
68 | SSYNC(); \ |
69 | } while (0) | |
70 | #define CONFIG_HOSTNAME bf533-stamp | |
71 | /* Uncomment next line to use fixed MAC address */ | |
72 | /* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ | |
3f0606ad | 73 | |
3f0606ad | 74 | |
ea818dbb HS |
75 | /* I2C */ |
76 | #define CONFIG_SYS_I2C | |
77 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
78 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
79 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0 | |
80 | /* | |
81 | * Software (bit-bang) I2C driver configuration | |
82 | */ | |
e5cb60a0 SZ |
83 | #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3 |
84 | #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2 | |
ea818dbb | 85 | |
3f0606ad | 86 | /* |
cf6f469e | 87 | * Flash Settings |
3f0606ad | 88 | */ |
cf6f469e MF |
89 | #define CONFIG_FLASH_CFI_DRIVER |
90 | #define CONFIG_SYS_FLASH_BASE 0x20000000 | |
91 | #define CONFIG_SYS_FLASH_CFI | |
92 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET | |
93 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
94 | #define CONFIG_SYS_MAX_FLASH_SECT 67 | |
3f0606ad | 95 | |
079a136c | 96 | /* |
cf6f469e | 97 | * SPI Settings |
079a136c | 98 | */ |
cf6f469e MF |
99 | #define CONFIG_BFIN_SPI |
100 | #define CONFIG_ENV_SPI_MAX_HZ 30000000 | |
c49eabef | 101 | /* |
afac8b07 | 102 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
cf6f469e | 103 | #define CONFIG_SPI_FLASH |
f453220c | 104 | #define CONFIG_SPI_FLASH_ALL |
c49eabef | 105 | */ |
079a136c | 106 | |
ba2351f9 | 107 | /* |
cf6f469e | 108 | * Env Storage Settings |
ba2351f9 | 109 | */ |
cf6f469e MF |
110 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
111 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
bc43a8d8 | 112 | #define CONFIG_ENV_OFFSET 0x10000 |
cf6f469e | 113 | #define CONFIG_ENV_SIZE 0x2000 |
bc43a8d8 | 114 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
cf6f469e MF |
115 | #else |
116 | #define CONFIG_ENV_IS_IN_FLASH | |
117 | #define CONFIG_ENV_OFFSET 0x4000 | |
118 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) | |
119 | #define CONFIG_ENV_SIZE 0x2000 | |
120 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
ba2351f9 | 121 | #endif |
cf6f469e MF |
122 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) |
123 | #define ENV_IS_EMBEDDED | |
3f0606ad | 124 | #else |
76d82187 | 125 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR |
3f0606ad | 126 | #endif |
9ff67e5e MF |
127 | #ifdef ENV_IS_EMBEDDED |
128 | /* WARNING - the following is hand-optimized to fit within | |
129 | * the sector before the environment sector. If it throws | |
130 | * an error during compilation remove an object here to get | |
131 | * it linked after the configuration sector. | |
132 | */ | |
133 | # define LDS_BOARD_TEXT \ | |
e2906a59 MY |
134 | arch/blackfin/lib/built-in.o (.text*); \ |
135 | arch/blackfin/cpu/built-in.o (.text*); \ | |
9ff67e5e | 136 | . = DEFINED(env_offset) ? env_offset : .; \ |
c70e7ddb | 137 | common/env_embedded.o (.text*); |
9ff67e5e | 138 | #endif |
3f0606ad | 139 | |
3f0606ad AL |
140 | |
141 | /* | |
cf6f469e | 142 | * I2C Settings |
3f0606ad | 143 | */ |
ea818dbb HS |
144 | #define CONFIG_SYS_I2C_SOFT |
145 | #ifdef CONFIG_SYS_I2C_SOFT | |
146 | #define CONFIG_SYS_I2C | |
beb60e77 MF |
147 | #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3 |
148 | #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2 | |
ea818dbb HS |
149 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
150 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
151 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0 | |
152 | #endif | |
3f0606ad AL |
153 | |
154 | /* | |
cf6f469e | 155 | * Compact Flash / IDE / ATA Settings |
3f0606ad AL |
156 | */ |
157 | ||
158 | /* Enabled below option for CF support */ | |
cf6f469e MF |
159 | /* #define CONFIG_STAMP_CF */ |
160 | #if defined(CONFIG_STAMP_CF) | |
161 | #define CONFIG_MISC_INIT_R | |
8db13d63 | 162 | #define CONFIG_DOS_PARTITION 1 |
8db13d63 AL |
163 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
164 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
165 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ | |
3f0606ad | 166 | |
cf6f469e MF |
167 | #define CONFIG_SYS_IDE_MAXBUS 1 |
168 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1) | |
3f0606ad | 169 | |
6d0f6bcf JCPV |
170 | #define CONFIG_SYS_ATA_BASE_ADDR 0x20200000 |
171 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
3f0606ad | 172 | |
cf6f469e MF |
173 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ |
174 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ | |
175 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */ | |
3f0606ad | 176 | |
6d0f6bcf | 177 | #define CONFIG_SYS_ATA_STRIDE 2 |
cf6f469e MF |
178 | |
179 | #undef CONFIG_EBIU_AMBCTL1_VAL | |
180 | #define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2 | |
3f0606ad AL |
181 | #endif |
182 | ||
cf6f469e | 183 | |
3f0606ad | 184 | /* |
cf6f469e | 185 | * Misc Settings |
3f0606ad | 186 | */ |
cf6f469e MF |
187 | #define CONFIG_RTC_BFIN |
188 | #define CONFIG_UART_CONSOLE 0 | |
3f0606ad | 189 | |
cf6f469e MF |
190 | /* FLASH/ETHERNET uses the same async bank */ |
191 | #define SHARED_RESOURCES 1 | |
3f0606ad | 192 | |
23fd959e MF |
193 | /* define to enable boot progress via leds */ |
194 | /* #define CONFIG_SHOW_BOOT_PROGRESS */ | |
195 | ||
196 | /* define to enable run status via led */ | |
197 | /* #define CONFIG_STATUS_LED */ | |
198 | #ifdef CONFIG_STATUS_LED | |
a84774f5 | 199 | #define CONFIG_GPIO_LED |
23fd959e | 200 | #define CONFIG_BOARD_SPECIFIC_LED |
a84774f5 | 201 | /* use LED0 to indicate booting/alive */ |
23fd959e | 202 | #define STATUS_LED_BOOT 0 |
a84774f5 | 203 | #define STATUS_LED_BIT GPIO_PF2 |
23fd959e MF |
204 | #define STATUS_LED_STATE STATUS_LED_ON |
205 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4) | |
a84774f5 | 206 | /* use LED1 to indicate crash */ |
23fd959e | 207 | #define STATUS_LED_CRASH 1 |
a84774f5 | 208 | #define STATUS_LED_BIT1 GPIO_PF3 |
23fd959e MF |
209 | #define STATUS_LED_STATE1 STATUS_LED_ON |
210 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) | |
a84774f5 | 211 | /* #define STATUS_LED_BIT2 GPIO_PF4 */ |
23fd959e MF |
212 | #endif |
213 | ||
cf6f469e MF |
214 | /* define to enable splash screen support */ |
215 | /* #define CONFIG_VIDEO */ | |
3f0606ad | 216 | |
3f0606ad AL |
217 | |
218 | /* | |
cf6f469e | 219 | * Pull in common ADI header for remaining command/environment setup |
3f0606ad | 220 | */ |
cf6f469e | 221 | #include <configs/bfin_adi_common.h> |
9171fc81 | 222 | |
3f0606ad | 223 | #endif |