[people/ms/u-boot.git] / include / configs / bf533-stamp.h

/*
 * U-boot - Configuration file for BF533 STAMP board
 */

#ifndef __CONFIG_STAMP_H__
#define __CONFIG_STAMP_H__

#include <asm/blackfin-config-pre.h>

#define CONFIG_RTC_BFIN			1

#define CONFIG_PANIC_HANG 1

#define CONFIG_BFIN_CPU	bf533-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS

/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
#define CONFIG_DCACHE_ON

/*
 * Board settings
 */
#define CONFIG_DRIVER_SMC91111	1
#define CONFIG_SMC91111_BASE	0x20300300

/* FLASH/ETHERNET uses the same address range */
#define SHARED_RESOURCES	1

/* Is I2C bit-banged? */
#define CONFIG_SOFT_I2C		1

/*
 * Software (bit-bang) I2C driver configuration
 */
#define PF_SCL			PF3
#define PF_SDA			PF2

/*
 * Video splash screen support
 */
#define  CONFIG_VIDEO		0

/*
 * Clock settings
 */

/* CONFIG_CLKIN_HZ is any value in Hz				*/
#define CONFIG_CLKIN_HZ		11059200
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
/*						    1=CLKIN/2	*/
#define CONFIG_CLKIN_HALF	0
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	*/
/*						 1=bypass PLL	*/
#define CONFIG_PLL_BYPASS	0
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	*/
/* Values can range from 1-64					*/
#define CONFIG_VCO_MULT		36
/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
/* Values can be 1, 2, 4, or 8 ONLY				*/
#define CONFIG_CCLK_DIV		1
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
/* Values can range from 1-15					*/
#define CONFIG_SCLK_DIV		5
/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
/* Values can range from 2-65535				*/
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
#define CONFIG_SPI_BAUD		2
#define CONFIG_SPI_BAUD_INITBLOCK	4

/*
 * Network settings
 */

#if (CONFIG_DRIVER_SMC91111)
#if 0
#define	CONFIG_MII
#endif

/* network support */
#define CONFIG_IPADDR		192.168.0.15
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_GATEWAYIP	192.168.0.1
#define CONFIG_SERVERIP		192.168.0.2
#define CONFIG_HOSTNAME		STAMP
#define CONFIG_ROOTPATH		/checkout/uClinux-dist/romfs

/* To remove hardcoding and enable MAC storage in EEPROM  */
/* #define CONFIG_ETHADDR		02:80:ad:20:31:b8 */
#endif /* CONFIG_DRIVER_SMC91111 */

/*
 * Flash settings
 */

#define CFG_FLASH_CFI		/* The flash is CFI compatible  */
#define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver	*/
#define	CFG_FLASH_CFI_AMD_RESET

#define CFG_FLASH_BASE		0x20000000
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */

#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_EEPROM	1
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_HEADER		(CONFIG_ENV_OFFSET + 0x12A)	/* 0x12A is the length of LDR file header */
#else
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		0x20004000
#define	CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CFG_FLASH_BASE)
#endif

#define	CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000	/* Total Size of Environment Sector */
#define	ENV_IS_EMBEDDED

#define CFG_FLASH_ERASE_TOUT	30000	/* Timeout for Chip Erase (in ms) */
#define CFG_FLASH_ERASEBLOCK_TOUT	5000	/* Timeout for Block Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms) */

/* JFFS Partition offset set  */
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_NUM_BANKS  1
/* 512k reserved for u-boot */
#define CFG_JFFS2_FIRST_SECTOR	11

/*
 * following timeouts shall be used once the
 * Flash real protection is enabled
 */
#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */

/*
 * SDRAM settings & memory map
 */

#define CONFIG_MEM_SIZE		128	/* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH     11	/* 8, 9, 10, 11    */
#define CONFIG_MEM_MT48LC64M4A2FB_7E	1

#define CFG_MEMTEST_START	0x00000000	/* memtest works on */

#define	CFG_SDRAM_BASE		0x00000000

#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 *1024)
#define CFG_MEMTEST_END		(CFG_MAX_RAM_SIZE - 0x80000 - 1)
#define CONFIG_LOADADDR		0x01000000

#define CFG_LOAD_ADDR		CONFIG_LOADADDR
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)     /* Reserve 128 kB for malloc()	*/
#define CFG_GBL_DATA_SIZE	0x4000		/* Reserve 16k for Global Data  */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */

#define CFG_MONITOR_BASE		(CFG_MAX_RAM_SIZE - 0x40000)
#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)

/* Check to make sure everything fits in SDRAM */
#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
	#error Memory Map does not fit into configuration
#endif

#if ( CONFIG_CLKIN_HALF == 0 )
#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
#else
#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
#endif

#if (CONFIG_PLL_BYPASS == 0)
#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
#else
#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
#endif

/*
 * Command settings
 */

#define CFG_LONGHELP		1
#define CONFIG_CMDLINE_EDITING	1

#define CFG_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */

/* configuration lookup from the BOOTP/DHCP server, */
/* but not try to load any image using TFTP	    */

#define CONFIG_BOOTDELAY	5
#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
#define CONFIG_BOOTCOMMAND	"run ramboot"

#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw console=ttyBF0,57600"


#define CONFIG_EXTRA_ENV_SETTINGS \
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
		"$(rootpath) console=ttyBF0,57600\0" \
	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
		"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
	"ramboot=tftpboot $(loadaddr) linux; " \
		"run ramargs;run addip;bootelf\0" \
	"nfsboot=tftpboot $(loadaddr) linux; " \
		"run nfsargs;run addip;bootelf\0" \
	"flashboot=bootm 0x20100000\0" \
	"update=tftpboot $(loadaddr) u-boot.bin; " \
		"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
		"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
	""

#ifdef CONFIG_SOFT_I2C
#if (!CONFIG_SOFT_I2C)
#undef CONFIG_SOFT_I2C
#endif
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ELF
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_DATE

#if (CONFIG_DRIVER_SMC91111)
#define CONFIG_CMD_PING
#endif

#if (CONFIG_SOFT_I2C)
#define CONFIG_CMD_I2C
#endif

#define CONFIG_CMD_DHCP


/*
 * Console settings
 */

#define CONFIG_BAUDRATE		57600
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define	CFG_PROMPT		"bfin> "	/* Monitor Command Prompt */

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_LOADS_ECHO	1

/*
 * I2C settings
 * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
 */
#if (CONFIG_SOFT_I2C)

#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
#define I2C_SDA(bit)	if(bit) { \
				*pFIO_FLAG_S = PF_SDA; \
				asm("ssync;"); \
				} \
			else	{ \
				*pFIO_FLAG_C = PF_SDA; \
				asm("ssync;"); \
				}
#define I2C_SCL(bit)	if(bit) { \
				*pFIO_FLAG_S = PF_SCL; \
				asm("ssync;"); \
				} \
			else	{ \
				*pFIO_FLAG_C = PF_SCL; \
				asm("ssync;"); \
				}
#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */

#define CFG_I2C_SPEED		50000
#define CFG_I2C_SLAVE		0xFE
#endif /* CONFIG_SOFT_I2C */

/*
 * Compact Flash settings
 */

/* Enabled below option for CF support */
/* #define CONFIG_STAMP_CF	1 */

#if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE)

#define CONFIG_MISC_INIT_R	1
#define CONFIG_DOS_PARTITION	1
/*
 * IDE/ATA stuff
 */
#undef  CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef  CONFIG_IDE_LED			/* no led for ide supported */
#undef  CONFIG_IDE_RESET		/* no reset for ide supported */

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses */
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	0x20200000
#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
#define CFG_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
#define CFG_ATA_ALT_OFFSET	0x0007	/* Offset for alternate registers */

#define CFG_ATA_STRIDE		2
#endif

/*
 * Miscellaneous configurable options
 */

#define	CFG_HZ			1000	/* 1ms time tick */

#define CFG_BOOTM_LEN		0x4000000/* Large Image Length, set to 64 Meg */

#define CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs */

#define CONFIG_SPI

#ifdef  CONFIG_VIDEO
#if (CONFIG_VIDEO)
#define CONFIG_SPLASH_SCREEN	1
#define CONFIG_SILENT_CONSOLE	1
#else
#undef CONFIG_VIDEO
#endif
#endif

/*
 * FLASH organization and environment definitions
 */

#define CONFIG_EBIU_SDRRC_VAL  0x268
#define CONFIG_EBIU_SDGCTL_VAL 0x911109
#define CONFIG_EBIU_SDBCTL_VAL 0x37

#define CONFIG_EBIU_AMGCTL_VAL		0xFF
#define CONFIG_EBIU_AMBCTL0_VAL		0xBBC3BBC3
#define CONFIG_EBIU_AMBCTL1_VAL		0x99B39983
#define CF_CONFIG_EBIU_AMBCTL1_VAL		0x99B3ffc2

#include <asm/blackfin-config-post.h>

#endif
Commit	Line	Data
3f0606ad AL	1	/*
	2	* U-boot - Configuration file for BF533 STAMP board
	3	*/
	4
	5	#ifndef __CONFIG_STAMP_H__
	6	#define __CONFIG_STAMP_H__
	7
f7ce12cb MF	8	#include <asm/blackfin-config-pre.h>
f7ce12cb MF	9
3f0606ad	10	#define CONFIG_RTC_BFIN 1
3f0606ad AL	11
	12	#define CONFIG_PANIC_HANG 1
	13
f7ce12cb	14	#define CONFIG_BFIN_CPU bf533-0.3
9171fc81	15	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
3f0606ad AL	16
	17	/* This sets the default state of the cache on U-Boot's boot */
	18	#define CONFIG_ICACHE_ON
	19	#define CONFIG_DCACHE_ON
	20
3f0606ad AL	21	/*
3f0606ad AL	22	* Board settings
3f0606ad	23	*/
8db13d63 AL	24	#define CONFIG_DRIVER_SMC91111 1
8db13d63 AL	25	#define CONFIG_SMC91111_BASE 0x20300300
3f0606ad AL	26
3f0606ad AL	27	/* FLASH/ETHERNET uses the same address range */
53677ef1	28	#define SHARED_RESOURCES 1
3f0606ad AL	29
3f0606ad AL	30	/* Is I2C bit-banged? */
8db13d63	31	#define CONFIG_SOFT_I2C 1
3f0606ad AL	32
	33	/*
	34	* Software (bit-bang) I2C driver configuration
	35	*/
8db13d63 AL	36	#define PF_SCL PF3
8db13d63 AL	37	#define PF_SDA PF2
3f0606ad AL	38
	39	/*
	40	* Video splash screen support
	41	*/
8db13d63	42	#define CONFIG_VIDEO 0
3f0606ad	43
3f0606ad AL	44	/*
3f0606ad AL	45	* Clock settings
3f0606ad AL	46	*/
3f0606ad AL	47
8db13d63 AL	48	/* CONFIG_CLKIN_HZ is any value in Hz */
	49	#define CONFIG_CLKIN_HZ 11059200
	50	/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
	51	/* 1=CLKIN/2 */
	52	#define CONFIG_CLKIN_HALF 0
	53	/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
	54	/* 1=bypass PLL */
	55	#define CONFIG_PLL_BYPASS 0
	56	/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
	57	/* Values can range from 1-64 */
	58	#define CONFIG_VCO_MULT 36
	59	/* CONFIG_CCLK_DIV controls what the core clock divider is */
	60	/* Values can be 1, 2, 4, or 8 ONLY */
	61	#define CONFIG_CCLK_DIV 1
	62	/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
	63	/* Values can range from 1-15 */
	64	#define CONFIG_SCLK_DIV 5
	65	/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
	66	/* Values can range from 2-65535 */
	67	/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
	68	#define CONFIG_SPI_BAUD 2
8db13d63	69	#define CONFIG_SPI_BAUD_INITBLOCK 4
3f0606ad	70
3f0606ad AL	71	/*
3f0606ad AL	72	* Network settings
3f0606ad AL	73	*/
	74
	75	#if (CONFIG_DRIVER_SMC91111)
	76	#if 0
	77	#define CONFIG_MII
	78	#endif
	79
	80	/* network support */
8db13d63 AL	81	#define CONFIG_IPADDR 192.168.0.15
	82	#define CONFIG_NETMASK 255.255.255.0
	83	#define CONFIG_GATEWAYIP 192.168.0.1
	84	#define CONFIG_SERVERIP 192.168.0.2
	85	#define CONFIG_HOSTNAME STAMP
	86	#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
3f0606ad AL	87
3f0606ad AL	88	/* To remove hardcoding and enable MAC storage in EEPROM */
8db13d63	89	/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
3f0606ad AL	90	#endif /* CONFIG_DRIVER_SMC91111 */
	91
	92	/*
	93	* Flash settings
3f0606ad AL	94	*/
3f0606ad AL	95
8db13d63	96	#define CFG_FLASH_CFI /* The flash is CFI compatible */
00b1883a	97	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
3f0606ad AL	98	#define CFG_FLASH_CFI_AMD_RESET
3f0606ad AL	99
8db13d63 AL	100	#define CFG_FLASH_BASE 0x20000000
	101	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	102	#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
3f0606ad	103
9171fc81	104	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
bb1f8b4f	105	#define CONFIG_ENV_IS_IN_EEPROM 1
0e8d1586 JCPV	106	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	107	#define CONFIG_ENV_HEADER (CONFIG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */
9171fc81	108	#else
5a1aceb0	109	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	110	#define CONFIG_ENV_ADDR 0x20004000
0e8d1586 JCPV	111	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CFG_FLASH_BASE)
3f0606ad AL	112	#endif
3f0606ad AL	113
0e8d1586 JCPV	114	#define CONFIG_ENV_SIZE 0x2000
0e8d1586 JCPV	115	#define CONFIG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
3f0606ad AL	116	#define ENV_IS_EMBEDDED
3f0606ad AL	117
8db13d63	118	#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
3f0606ad	119	#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
8db13d63	120	#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
3f0606ad AL	121
	122	/* JFFS Partition offset set */
	123	#define CFG_JFFS2_FIRST_BANK 0
	124	#define CFG_JFFS2_NUM_BANKS 1
	125	/* 512k reserved for u-boot */
53677ef1	126	#define CFG_JFFS2_FIRST_SECTOR 11
3f0606ad AL	127
	128	/*
	129	* following timeouts shall be used once the
	130	* Flash real protection is enabled
	131	*/
8db13d63 AL	132	#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
8db13d63 AL	133	#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
3f0606ad AL	134
	135	/*
	136	* SDRAM settings & memory map
3f0606ad AL	137	*/
3f0606ad AL	138
8db13d63 AL	139	#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
8db13d63 AL	140	#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
3f0606ad AL	141	#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
3f0606ad AL	142
8db13d63	143	#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
3f0606ad	144
8db13d63	145	#define CFG_SDRAM_BASE 0x00000000
3f0606ad AL	146
	147	#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024)
	148	#define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1)
	149	#define CONFIG_LOADADDR 0x01000000
	150
53677ef1	151	#define CFG_LOAD_ADDR CONFIG_LOADADDR
8db13d63 AL	152	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	153	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	154	#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
	155	#define CONFIG_STACKSIZE (1281024) / regular stack */
3f0606ad AL	156
3f0606ad AL	157	#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - 0x40000)
8db13d63 AL	158	#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
	159	#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
	160	#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
3f0606ad AL	161
	162	/* Check to make sure everything fits in SDRAM */
	163	#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
	164	#error Memory Map does not fit into configuration
	165	#endif
	166
	167	#if ( CONFIG_CLKIN_HALF == 0 )
8db13d63	168	#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
3f0606ad	169	#else
8db13d63	170	#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
3f0606ad AL	171	#endif
	172
	173	#if (CONFIG_PLL_BYPASS == 0)
8db13d63 AL	174	#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
8db13d63 AL	175	#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
3f0606ad	176	#else
8db13d63 AL	177	#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
8db13d63 AL	178	#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
3f0606ad AL	179	#endif
3f0606ad AL	180
3f0606ad AL	181	/*
3f0606ad AL	182	* Command settings
3f0606ad AL	183	*/
3f0606ad AL	184
8db13d63 AL	185	#define CFG_LONGHELP 1
8db13d63 AL	186	#define CONFIG_CMDLINE_EDITING 1
3f0606ad	187
8db13d63	188	#define CFG_AUTOLOAD "no" /rarpb, bootp or dhcp commands will perform only a /
3f0606ad	189
8db13d63	190	/* configuration lookup from the BOOTP/DHCP server, */
0d93de11	191	/* but not try to load any image using TFTP */
8db13d63 AL	192
	193	#define CONFIG_BOOTDELAY 5
	194	#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
8db13d63	195	#define CONFIG_BOOTCOMMAND "run ramboot"
3f0606ad	196
8db13d63	197	#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
3f0606ad	198
3f0606ad	199
3f0606ad	200	#define CONFIG_EXTRA_ENV_SETTINGS \
8db13d63 AL	201	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	202	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
	203	"$(rootpath) console=ttyBF0,57600\0" \
	204	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
	205	"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
	206	"ramboot=tftpboot $(loadaddr) linux; " \
3f0606ad	207	"run ramargs;run addip;bootelf\0" \
8db13d63	208	"nfsboot=tftpboot $(loadaddr) linux; " \
3f0606ad	209	"run nfsargs;run addip;bootelf\0" \
8db13d63 AL	210	"flashboot=bootm 0x20100000\0" \
	211	"update=tftpboot $(loadaddr) u-boot.bin; " \
	212	"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
	213	"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
	214	""
3f0606ad AL	215
	216	#ifdef CONFIG_SOFT_I2C
	217	#if (!CONFIG_SOFT_I2C)
	218	#undef CONFIG_SOFT_I2C
	219	#endif
	220	#endif
	221
ba2351f9	222
079a136c JL	223	/*
	224	* BOOTP options
	225	*/
	226	#define CONFIG_BOOTP_BOOTFILESIZE
	227	#define CONFIG_BOOTP_BOOTPATH
	228	#define CONFIG_BOOTP_GATEWAY
	229	#define CONFIG_BOOTP_HOSTNAME
	230
	231
ba2351f9 JL	232	/*
	233	* Command line configuration.
	234	*/
	235	#include <config_cmd_default.h>
	236
	237	#define CONFIG_CMD_ELF
	238	#define CONFIG_CMD_CACHE
	239	#define CONFIG_CMD_JFFS2
	240	#define CONFIG_CMD_EEPROM
	241	#define CONFIG_CMD_DATE
	242
	243	#if (CONFIG_DRIVER_SMC91111)
	244	#define CONFIG_CMD_PING
	245	#endif
	246
3f0606ad	247	#if (CONFIG_SOFT_I2C)
ba2351f9 JL	248	#define CONFIG_CMD_I2C
ba2351f9 JL	249	#endif
3f0606ad	250
ba2351f9	251	#define CONFIG_CMD_DHCP
3f0606ad	252
3f0606ad AL	253
	254	/*
	255	* Console settings
3f0606ad AL	256	*/
3f0606ad AL	257
8db13d63 AL	258	#define CONFIG_BAUDRATE 57600
8db13d63 AL	259	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
3f0606ad	260
f7ce12cb	261	#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */
3f0606ad	262
ba2351f9	263	#if defined(CONFIG_CMD_KGDB)
8db13d63	264	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
3f0606ad	265	#else
8db13d63	266	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
3f0606ad	267	#endif
8db13d63 AL	268	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	269	#define CFG_MAXARGS 16 /* max number of command args */
	270	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
3f0606ad	271
8db13d63	272	#define CONFIG_LOADS_ECHO 1
3f0606ad AL	273
	274	/*
	275	* I2C settings
	276	* By default PF2 is used as SDA and PF3 as SCL on the Stamp board
	277	*/
	278	#if (CONFIG_SOFT_I2C)
	279
8db13d63 AL	280	#define I2C_INIT (*pFIO_DIR \|= PF_SCL); asm("ssync;")
	281	#define I2C_ACTIVE (pFIO_DIR \|= PF_SDA); pFIO_INEN &= ~PF_SDA; asm("ssync;")
	282	#define I2C_TRISTATE (pFIO_DIR &= ~PF_SDA); pFIO_INEN \|= PF_SDA; asm("ssync;")
	283	#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
	284	#define I2C_SDA(bit) if(bit) { \
	285	*pFIO_FLAG_S = PF_SDA; \
	286	asm("ssync;"); \
	287	} \
	288	else { \
	289	*pFIO_FLAG_C = PF_SDA; \
	290	asm("ssync;"); \
	291	}
	292	#define I2C_SCL(bit) if(bit) { \
	293	*pFIO_FLAG_S = PF_SCL; \
	294	asm("ssync;"); \
	295	} \
	296	else { \
	297	*pFIO_FLAG_C = PF_SCL; \
	298	asm("ssync;"); \
	299	}
	300	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	301
	302	#define CFG_I2C_SPEED 50000
	303	#define CFG_I2C_SLAVE 0xFE
3f0606ad AL	304	#endif /* CONFIG_SOFT_I2C */
	305
	306	/*
	307	* Compact Flash settings
	308	*/
	309
	310	/* Enabled below option for CF support */
8db13d63	311	/* #define CONFIG_STAMP_CF 1 */
3f0606ad	312
ba2351f9	313	#if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE)
3f0606ad	314
8db13d63 AL	315	#define CONFIG_MISC_INIT_R 1
8db13d63 AL	316	#define CONFIG_DOS_PARTITION 1
3f0606ad AL	317	/*
	318	* IDE/ATA stuff
	319	*/
8db13d63 AL	320	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	321	#undef CONFIG_IDE_LED /* no led for ide supported */
	322	#undef CONFIG_IDE_RESET /* no reset for ide supported */
3f0606ad	323
8db13d63 AL	324	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
8db13d63 AL	325	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS1) / max. 1 drives per IDE bus */
3f0606ad	326
8db13d63 AL	327	#define CFG_ATA_BASE_ADDR 0x20200000
8db13d63 AL	328	#define CFG_ATA_IDE0_OFFSET 0x0000
3f0606ad	329
8db13d63 AL	330	#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
	331	#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
	332	#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
3f0606ad	333
8db13d63	334	#define CFG_ATA_STRIDE 2
3f0606ad AL	335	#endif
	336
	337	/*
	338	* Miscellaneous configurable options
	339	*/
	340
8db13d63	341	#define CFG_HZ 1000 /* 1ms time tick */
3f0606ad	342
8db13d63	343	#define CFG_BOOTM_LEN 0x4000000/* Large Image Length, set to 64 Meg */
3f0606ad	344
8db13d63	345	#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
3f0606ad AL	346
	347	#define CONFIG_SPI
	348
	349	#ifdef CONFIG_VIDEO
	350	#if (CONFIG_VIDEO)
8db13d63 AL	351	#define CONFIG_SPLASH_SCREEN 1
8db13d63 AL	352	#define CONFIG_SILENT_CONSOLE 1
3f0606ad AL	353	#else
	354	#undef CONFIG_VIDEO
	355	#endif
	356	#endif
	357
	358	/*
	359	* FLASH organization and environment definitions
	360	*/
9171fc81 MF	361
	362	#define CONFIG_EBIU_SDRRC_VAL 0x268
	363	#define CONFIG_EBIU_SDGCTL_VAL 0x911109
	364	#define CONFIG_EBIU_SDBCTL_VAL 0x37
	365
	366	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	367	#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
	368	#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
	369	#define CF_CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
	370
	371	#include <asm/blackfin-config-post.h>
3f0606ad	372
3f0606ad	373	#endif