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Commit | Line | Data |
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3f0606ad AL |
1 | /* |
2 | * U-boot - Configuration file for BF533 STAMP board | |
3 | */ | |
4 | ||
cf6f469e MF |
5 | #ifndef __CONFIG_BF533_STAMP_H__ |
6 | #define __CONFIG_BF533_STAMP_H__ | |
3f0606ad | 7 | |
f348ab85 | 8 | #include <asm/config-pre.h> |
f7ce12cb | 9 | |
3f0606ad | 10 | |
3f0606ad | 11 | /* |
cf6f469e | 12 | * Processor Settings |
3f0606ad | 13 | */ |
fbcf8e8c | 14 | #define CONFIG_BFIN_CPU bf533-0.3 |
cf6f469e | 15 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS |
3f0606ad | 16 | |
3f0606ad AL |
17 | |
18 | /* | |
cf6f469e MF |
19 | * Clock Settings |
20 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV | |
21 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV | |
3f0606ad | 22 | */ |
cf6f469e MF |
23 | /* CONFIG_CLKIN_HZ is any value in Hz */ |
24 | #define CONFIG_CLKIN_HZ 11059200 | |
25 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ | |
26 | /* 1 = CLKIN / 2 */ | |
27 | #define CONFIG_CLKIN_HALF 0 | |
28 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ | |
29 | /* 1 = bypass PLL */ | |
30 | #define CONFIG_PLL_BYPASS 0 | |
31 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ | |
32 | /* Values can range from 0-63 (where 0 means 64) */ | |
9f64ba24 | 33 | #define CONFIG_VCO_MULT 45 |
cf6f469e MF |
34 | /* CCLK_DIV controls the core clock divider */ |
35 | /* Values can be 1, 2, 4, or 8 ONLY */ | |
36 | #define CONFIG_CCLK_DIV 1 | |
37 | /* SCLK_DIV controls the system clock divider */ | |
38 | /* Values can range from 1-15 */ | |
baf35705 | 39 | #define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */ |
3f0606ad | 40 | |
3f0606ad | 41 | |
3f0606ad | 42 | /* |
cf6f469e | 43 | * Memory Settings |
3f0606ad | 44 | */ |
cf6f469e MF |
45 | #define CONFIG_MEM_ADD_WDTH 11 |
46 | #define CONFIG_MEM_SIZE 128 | |
3f0606ad | 47 | |
cf6f469e MF |
48 | #define CONFIG_EBIU_SDRRC_VAL 0x268 |
49 | #define CONFIG_EBIU_SDGCTL_VAL 0x911109 | |
3f0606ad | 50 | |
cf6f469e MF |
51 | #define CONFIG_EBIU_AMGCTL_VAL 0xFF |
52 | #define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3 | |
53 | #define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983 | |
3f0606ad | 54 | |
cf6f469e MF |
55 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
56 | #define CONFIG_SYS_MALLOC_LEN (384 * 1024) | |
3f0606ad | 57 | |
3f0606ad AL |
58 | |
59 | /* | |
cf6f469e | 60 | * Network Settings |
3f0606ad | 61 | */ |
cf6f469e | 62 | #define ADI_CMDS_NETWORK 1 |
7194ab80 | 63 | #define CONFIG_SMC91111 1 |
cf6f469e MF |
64 | #define CONFIG_SMC91111_BASE 0x20300300 |
65 | #define SMC91111_EEPROM_INIT() \ | |
66 | do { \ | |
7194ab80 BW |
67 | bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \ |
68 | bfin_write_FIO_FLAG_C(PF1); \ | |
69 | bfin_write_FIO_FLAG_S(PF0); \ | |
cf6f469e MF |
70 | SSYNC(); \ |
71 | } while (0) | |
72 | #define CONFIG_HOSTNAME bf533-stamp | |
73 | /* Uncomment next line to use fixed MAC address */ | |
74 | /* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ | |
3f0606ad | 75 | |
3f0606ad | 76 | |
3f0606ad | 77 | /* |
cf6f469e | 78 | * Flash Settings |
3f0606ad | 79 | */ |
cf6f469e MF |
80 | #define CONFIG_FLASH_CFI_DRIVER |
81 | #define CONFIG_SYS_FLASH_BASE 0x20000000 | |
82 | #define CONFIG_SYS_FLASH_CFI | |
83 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET | |
84 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
85 | #define CONFIG_SYS_MAX_FLASH_SECT 67 | |
3f0606ad | 86 | |
ba2351f9 | 87 | |
079a136c | 88 | /* |
cf6f469e | 89 | * SPI Settings |
079a136c | 90 | */ |
cf6f469e MF |
91 | #define CONFIG_BFIN_SPI |
92 | #define CONFIG_ENV_SPI_MAX_HZ 30000000 | |
afac8b07 | 93 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
cf6f469e | 94 | #define CONFIG_SPI_FLASH |
f453220c | 95 | #define CONFIG_SPI_FLASH_ALL |
079a136c JL |
96 | |
97 | ||
ba2351f9 | 98 | /* |
cf6f469e | 99 | * Env Storage Settings |
ba2351f9 | 100 | */ |
cf6f469e MF |
101 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
102 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
bc43a8d8 | 103 | #define CONFIG_ENV_OFFSET 0x10000 |
cf6f469e | 104 | #define CONFIG_ENV_SIZE 0x2000 |
bc43a8d8 | 105 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
cf6f469e MF |
106 | #else |
107 | #define CONFIG_ENV_IS_IN_FLASH | |
108 | #define CONFIG_ENV_OFFSET 0x4000 | |
109 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) | |
110 | #define CONFIG_ENV_SIZE 0x2000 | |
111 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
ba2351f9 | 112 | #endif |
cf6f469e MF |
113 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) |
114 | #define ENV_IS_EMBEDDED | |
3f0606ad | 115 | #else |
76d82187 | 116 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR |
3f0606ad | 117 | #endif |
9ff67e5e MF |
118 | #ifdef ENV_IS_EMBEDDED |
119 | /* WARNING - the following is hand-optimized to fit within | |
120 | * the sector before the environment sector. If it throws | |
121 | * an error during compilation remove an object here to get | |
122 | * it linked after the configuration sector. | |
123 | */ | |
124 | # define LDS_BOARD_TEXT \ | |
c70e7ddb MF |
125 | arch/blackfin/lib/libblackfin.o (.text*); \ |
126 | arch/blackfin/cpu/libblackfin.o (.text*); \ | |
9ff67e5e | 127 | . = DEFINED(env_offset) ? env_offset : .; \ |
c70e7ddb | 128 | common/env_embedded.o (.text*); |
9ff67e5e | 129 | #endif |
3f0606ad | 130 | |
3f0606ad AL |
131 | |
132 | /* | |
cf6f469e | 133 | * I2C Settings |
3f0606ad | 134 | */ |
cf6f469e | 135 | #define CONFIG_SOFT_I2C |
beb60e77 MF |
136 | #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3 |
137 | #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2 | |
cf6f469e | 138 | |
3f0606ad AL |
139 | |
140 | /* | |
cf6f469e | 141 | * Compact Flash / IDE / ATA Settings |
3f0606ad AL |
142 | */ |
143 | ||
144 | /* Enabled below option for CF support */ | |
cf6f469e MF |
145 | /* #define CONFIG_STAMP_CF */ |
146 | #if defined(CONFIG_STAMP_CF) | |
147 | #define CONFIG_MISC_INIT_R | |
8db13d63 | 148 | #define CONFIG_DOS_PARTITION 1 |
8db13d63 AL |
149 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
150 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
151 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ | |
3f0606ad | 152 | |
cf6f469e MF |
153 | #define CONFIG_SYS_IDE_MAXBUS 1 |
154 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1) | |
3f0606ad | 155 | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_ATA_BASE_ADDR 0x20200000 |
157 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
3f0606ad | 158 | |
cf6f469e MF |
159 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ |
160 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ | |
161 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */ | |
3f0606ad | 162 | |
6d0f6bcf | 163 | #define CONFIG_SYS_ATA_STRIDE 2 |
cf6f469e MF |
164 | |
165 | #undef CONFIG_EBIU_AMBCTL1_VAL | |
166 | #define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2 | |
3f0606ad AL |
167 | #endif |
168 | ||
cf6f469e | 169 | |
3f0606ad | 170 | /* |
cf6f469e | 171 | * Misc Settings |
3f0606ad | 172 | */ |
cf6f469e MF |
173 | #define CONFIG_RTC_BFIN |
174 | #define CONFIG_UART_CONSOLE 0 | |
3f0606ad | 175 | |
cf6f469e MF |
176 | /* FLASH/ETHERNET uses the same async bank */ |
177 | #define SHARED_RESOURCES 1 | |
3f0606ad | 178 | |
23fd959e MF |
179 | /* define to enable boot progress via leds */ |
180 | /* #define CONFIG_SHOW_BOOT_PROGRESS */ | |
181 | ||
182 | /* define to enable run status via led */ | |
183 | /* #define CONFIG_STATUS_LED */ | |
184 | #ifdef CONFIG_STATUS_LED | |
a84774f5 | 185 | #define CONFIG_GPIO_LED |
23fd959e | 186 | #define CONFIG_BOARD_SPECIFIC_LED |
a84774f5 | 187 | /* use LED0 to indicate booting/alive */ |
23fd959e | 188 | #define STATUS_LED_BOOT 0 |
a84774f5 | 189 | #define STATUS_LED_BIT GPIO_PF2 |
23fd959e MF |
190 | #define STATUS_LED_STATE STATUS_LED_ON |
191 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4) | |
a84774f5 | 192 | /* use LED1 to indicate crash */ |
23fd959e | 193 | #define STATUS_LED_CRASH 1 |
a84774f5 | 194 | #define STATUS_LED_BIT1 GPIO_PF3 |
23fd959e MF |
195 | #define STATUS_LED_STATE1 STATUS_LED_ON |
196 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) | |
a84774f5 | 197 | /* #define STATUS_LED_BIT2 GPIO_PF4 */ |
23fd959e MF |
198 | #endif |
199 | ||
cf6f469e MF |
200 | /* define to enable splash screen support */ |
201 | /* #define CONFIG_VIDEO */ | |
3f0606ad | 202 | |
3f0606ad AL |
203 | |
204 | /* | |
cf6f469e | 205 | * Pull in common ADI header for remaining command/environment setup |
3f0606ad | 206 | */ |
cf6f469e | 207 | #include <configs/bfin_adi_common.h> |
9171fc81 | 208 | |
3f0606ad | 209 | #endif |