[people/ms/u-boot.git] / include / configs / bf533-stamp.h

/*
 * U-boot - Configuration file for BF533 STAMP board
 */

#ifndef __CONFIG_BF533_STAMP_H__
#define __CONFIG_BF533_STAMP_H__

#include <asm/config-pre.h>


/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf533-0.3
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS

/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			11059200
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			45
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			6 /* note: 1.2 boards can go faster */

/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	11
#define CONFIG_MEM_SIZE		128

#define CONFIG_EBIU_SDRRC_VAL	0x268
#define CONFIG_EBIU_SDGCTL_VAL	0x911109

#define CONFIG_EBIU_AMGCTL_VAL	0xFF
#define CONFIG_EBIU_AMBCTL0_VAL	0xBBC3BBC3
#define CONFIG_EBIU_AMBCTL1_VAL	0x99B39983

#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(384 * 1024)


/*
 * Network Settings
 */
#define ADI_CMDS_NETWORK	1
#define CONFIG_SMC91111	1
#define CONFIG_SMC91111_BASE	0x20300300
#define SMC91111_EEPROM_INIT() \
	do { \
		bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
		bfin_write_FIO_FLAG_C(PF1); \
		bfin_write_FIO_FLAG_S(PF0); \
		SSYNC(); \
	} while (0)
#define CONFIG_HOSTNAME		bf533-stamp
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR	02:80:ad:20:31:b8 */


/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PF_SCL			PF3
#define PF_SDA			PF2
#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); \
				*pFIO_INEN &= ~PF_SDA; asm("ssync;")
#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); \
				*pFIO_INEN |= PF_SDA; asm("ssync;")
#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); \
				asm("ssync;")
#define I2C_SDA(bit)	if (bit) { \
				*pFIO_FLAG_S = PF_SDA; \
				asm("ssync;"); \
				} \
			else	{ \
				*pFIO_FLAG_C = PF_SDA; \
				asm("ssync;"); \
				}
#define I2C_SCL(bit)	if (bit) { \
				*pFIO_FLAG_S = PF_SCL; \
				asm("ssync;"); \
				} \
			else	{ \
				*pFIO_FLAG_C = PF_SCL; \
				asm("ssync;"); \
				}
#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */


/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_AMD_RESET
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	67

/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_SF_DEFAULT_SPEED	30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ALL


/*
 * Env Storage Settings
 */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x10000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET	0x4000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000
#endif
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
 * the sector before the environment sector. If it throws
 * an error during compilation remove an object here to get
 * it linked after the configuration sector.
 */
# define LDS_BOARD_TEXT \
	arch/blackfin/lib/libblackfin.o (.text*); \
	arch/blackfin/cpu/libblackfin.o (.text*); \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o (.text*);
#endif


/*
 * I2C Settings
 */
#define CONFIG_SYS_I2C_SOFT
#ifdef CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0
#endif

/*
 * Compact Flash / IDE / ATA Settings
 */

/* Enabled below option for CF support */
/* #define CONFIG_STAMP_CF */
#if defined(CONFIG_STAMP_CF)
#define CONFIG_MISC_INIT_R
#define CONFIG_DOS_PARTITION	1
#undef  CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef  CONFIG_IDE_LED			/* no led for ide supported */
#undef  CONFIG_IDE_RESET		/* no reset for ide supported */

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS * 1)

#define CONFIG_SYS_ATA_BASE_ADDR	0x20200000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0007	/* alternate registers */

#define CONFIG_SYS_ATA_STRIDE		2

#undef CONFIG_EBIU_AMBCTL1_VAL
#define CONFIG_EBIU_AMBCTL1_VAL	0x99B3ffc2
#endif


/*
 * Misc Settings
 */
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	0

/* FLASH/ETHERNET uses the same async bank */
#define SHARED_RESOURCES 	1

/* define to enable boot progress via leds */
/* #define CONFIG_SHOW_BOOT_PROGRESS */

/* define to enable run status via led */
/* #define CONFIG_STATUS_LED */
#ifdef CONFIG_STATUS_LED
#define CONFIG_GPIO_LED
#define CONFIG_BOARD_SPECIFIC_LED
/* use LED0 to indicate booting/alive */
#define STATUS_LED_BOOT 0
#define STATUS_LED_BIT GPIO_PF2
#define STATUS_LED_STATE STATUS_LED_ON
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
/* use LED1 to indicate crash */
#define STATUS_LED_CRASH 1
#define STATUS_LED_BIT1 GPIO_PF3
#define STATUS_LED_STATE1 STATUS_LED_ON
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
/* #define STATUS_LED_BIT2 GPIO_PF4 */
#endif

/* define to enable splash screen support */
/* #define CONFIG_VIDEO */


/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
3f0606ad AL	1	/*
	2	* U-boot - Configuration file for BF533 STAMP board
	3	*/
	4
cf6f469e MF	5	#ifndef __CONFIG_BF533_STAMP_H__
cf6f469e MF	6	#define __CONFIG_BF533_STAMP_H__
3f0606ad	7
f348ab85	8	#include <asm/config-pre.h>
f7ce12cb	9
3f0606ad	10
3f0606ad	11	/*
cf6f469e	12	* Processor Settings
3f0606ad	13	*/
fbcf8e8c	14	#define CONFIG_BFIN_CPU bf533-0.3
cf6f469e	15	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
3f0606ad	16
3f0606ad	17	/*
cf6f469e MF	18	* Clock Settings
	19	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	20	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
3f0606ad	21	*/
cf6f469e MF	22	/* CONFIG_CLKIN_HZ is any value in Hz */
	23	#define CONFIG_CLKIN_HZ 11059200
	24	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	25	/* 1 = CLKIN / 2 */
	26	#define CONFIG_CLKIN_HALF 0
	27	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	28	/* 1 = bypass PLL */
	29	#define CONFIG_PLL_BYPASS 0
	30	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	31	/* Values can range from 0-63 (where 0 means 64) */
9f64ba24	32	#define CONFIG_VCO_MULT 45
cf6f469e MF	33	/* CCLK_DIV controls the core clock divider */
	34	/* Values can be 1, 2, 4, or 8 ONLY */
	35	#define CONFIG_CCLK_DIV 1
	36	/* SCLK_DIV controls the system clock divider */
	37	/* Values can range from 1-15 */
baf35705	38	#define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
3f0606ad	39
3f0606ad	40	/*
cf6f469e	41	* Memory Settings
3f0606ad	42	*/
cf6f469e MF	43	#define CONFIG_MEM_ADD_WDTH 11
cf6f469e MF	44	#define CONFIG_MEM_SIZE 128
3f0606ad	45
cf6f469e MF	46	#define CONFIG_EBIU_SDRRC_VAL 0x268
cf6f469e MF	47	#define CONFIG_EBIU_SDGCTL_VAL 0x911109
3f0606ad	48
cf6f469e MF	49	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	50	#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
	51	#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
3f0606ad	52
cf6f469e MF	53	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
cf6f469e MF	54	#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
3f0606ad	55
3f0606ad AL	56
3f0606ad AL	57	/*
cf6f469e	58	* Network Settings
3f0606ad	59	*/
cf6f469e	60	#define ADI_CMDS_NETWORK 1
7194ab80	61	#define CONFIG_SMC91111 1
cf6f469e MF	62	#define CONFIG_SMC91111_BASE 0x20300300
	63	#define SMC91111_EEPROM_INIT() \
	64	do { \
7194ab80 BW	65	bfin_write_FIO_DIR(bfin_read_FIO_DIR() \| PF1 \| PF0); \
	66	bfin_write_FIO_FLAG_C(PF1); \
	67	bfin_write_FIO_FLAG_S(PF0); \
cf6f469e MF	68	SSYNC(); \
	69	} while (0)
	70	#define CONFIG_HOSTNAME bf533-stamp
	71	/* Uncomment next line to use fixed MAC address */
	72	/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
3f0606ad	73
3f0606ad	74
ea818dbb HS	75	/* I2C */
	76	#define CONFIG_SYS_I2C
	77	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	78	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	79	#define CONFIG_SYS_I2C_SOFT_SLAVE 0
	80	/*
	81	* Software (bit-bang) I2C driver configuration
	82	*/
	83	#define PF_SCL PF3
	84	#define PF_SDA PF2
	85	#define I2C_INIT (*pFIO_DIR \|= PF_SCL); asm("ssync;")
	86	#define I2C_ACTIVE (*pFIO_DIR \|= PF_SDA); \
	87	*pFIO_INEN &= ~PF_SDA; asm("ssync;")
	88	#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); \
	89	*pFIO_INEN \|= PF_SDA; asm("ssync;")
	90	#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); \
	91	asm("ssync;")
	92	#define I2C_SDA(bit) if (bit) { \
	93	*pFIO_FLAG_S = PF_SDA; \
	94	asm("ssync;"); \
	95	} \
	96	else { \
	97	*pFIO_FLAG_C = PF_SDA; \
	98	asm("ssync;"); \
	99	}
	100	#define I2C_SCL(bit) if (bit) { \
	101	*pFIO_FLAG_S = PF_SCL; \
	102	asm("ssync;"); \
	103	} \
	104	else { \
	105	*pFIO_FLAG_C = PF_SCL; \
	106	asm("ssync;"); \
	107	}
	108	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	109
	110
3f0606ad	111	/*
cf6f469e	112	* Flash Settings
3f0606ad	113	*/
cf6f469e MF	114	#define CONFIG_FLASH_CFI_DRIVER
	115	#define CONFIG_SYS_FLASH_BASE 0x20000000
	116	#define CONFIG_SYS_FLASH_CFI
	117	#define CONFIG_SYS_FLASH_CFI_AMD_RESET
	118	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	119	#define CONFIG_SYS_MAX_FLASH_SECT 67
3f0606ad	120
079a136c	121	/*
cf6f469e	122	* SPI Settings
079a136c	123	*/
cf6f469e MF	124	#define CONFIG_BFIN_SPI
cf6f469e MF	125	#define CONFIG_ENV_SPI_MAX_HZ 30000000
afac8b07	126	#define CONFIG_SF_DEFAULT_SPEED 30000000
cf6f469e	127	#define CONFIG_SPI_FLASH
f453220c	128	#define CONFIG_SPI_FLASH_ALL
079a136c JL	129
079a136c JL	130
ba2351f9	131	/*
cf6f469e	132	* Env Storage Settings
ba2351f9	133	*/
cf6f469e MF	134	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
cf6f469e MF	135	#define CONFIG_ENV_IS_IN_SPI_FLASH
bc43a8d8	136	#define CONFIG_ENV_OFFSET 0x10000
cf6f469e	137	#define CONFIG_ENV_SIZE 0x2000
bc43a8d8	138	#define CONFIG_ENV_SECT_SIZE 0x10000
cf6f469e MF	139	#else
	140	#define CONFIG_ENV_IS_IN_FLASH
	141	#define CONFIG_ENV_OFFSET 0x4000
	142	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	143	#define CONFIG_ENV_SIZE 0x2000
	144	#define CONFIG_ENV_SECT_SIZE 0x2000
ba2351f9	145	#endif
cf6f469e MF	146	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
cf6f469e MF	147	#define ENV_IS_EMBEDDED
3f0606ad	148	#else
76d82187	149	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
3f0606ad	150	#endif
9ff67e5e MF	151	#ifdef ENV_IS_EMBEDDED
	152	/* WARNING - the following is hand-optimized to fit within
	153	* the sector before the environment sector. If it throws
	154	* an error during compilation remove an object here to get
	155	* it linked after the configuration sector.
	156	*/
	157	# define LDS_BOARD_TEXT \
c70e7ddb MF	158	arch/blackfin/lib/libblackfin.o (.text*); \
c70e7ddb MF	159	arch/blackfin/cpu/libblackfin.o (.text*); \
9ff67e5e	160	. = DEFINED(env_offset) ? env_offset : .; \
c70e7ddb	161	common/env_embedded.o (.text*);
9ff67e5e	162	#endif
3f0606ad	163
3f0606ad AL	164
3f0606ad AL	165	/*
cf6f469e	166	* I2C Settings
3f0606ad	167	*/
ea818dbb HS	168	#define CONFIG_SYS_I2C_SOFT
	169	#ifdef CONFIG_SYS_I2C_SOFT
	170	#define CONFIG_SYS_I2C
beb60e77 MF	171	#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
beb60e77 MF	172	#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
ea818dbb HS	173	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	174	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	175	#define CONFIG_SYS_I2C_SOFT_SLAVE 0
	176	#endif
3f0606ad AL	177
3f0606ad AL	178	/*
cf6f469e	179	* Compact Flash / IDE / ATA Settings
3f0606ad AL	180	*/
	181
	182	/* Enabled below option for CF support */
cf6f469e MF	183	/* #define CONFIG_STAMP_CF */
	184	#if defined(CONFIG_STAMP_CF)
	185	#define CONFIG_MISC_INIT_R
8db13d63	186	#define CONFIG_DOS_PARTITION 1
8db13d63 AL	187	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	188	#undef CONFIG_IDE_LED /* no led for ide supported */
	189	#undef CONFIG_IDE_RESET /* no reset for ide supported */
3f0606ad	190
cf6f469e MF	191	#define CONFIG_SYS_IDE_MAXBUS 1
cf6f469e MF	192	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
3f0606ad	193
6d0f6bcf JCPV	194	#define CONFIG_SYS_ATA_BASE_ADDR 0x20200000
6d0f6bcf JCPV	195	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
3f0606ad	196
cf6f469e MF	197	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
	198	#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
	199	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */
3f0606ad	200
6d0f6bcf	201	#define CONFIG_SYS_ATA_STRIDE 2
cf6f469e MF	202
	203	#undef CONFIG_EBIU_AMBCTL1_VAL
	204	#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
3f0606ad AL	205	#endif
3f0606ad AL	206
cf6f469e	207
3f0606ad	208	/*
cf6f469e	209	* Misc Settings
3f0606ad	210	*/
cf6f469e MF	211	#define CONFIG_RTC_BFIN
cf6f469e MF	212	#define CONFIG_UART_CONSOLE 0
3f0606ad	213
cf6f469e MF	214	/* FLASH/ETHERNET uses the same async bank */
cf6f469e MF	215	#define SHARED_RESOURCES 1
3f0606ad	216
23fd959e MF	217	/* define to enable boot progress via leds */
	218	/* #define CONFIG_SHOW_BOOT_PROGRESS */
	219
	220	/* define to enable run status via led */
	221	/* #define CONFIG_STATUS_LED */
	222	#ifdef CONFIG_STATUS_LED
a84774f5	223	#define CONFIG_GPIO_LED
23fd959e	224	#define CONFIG_BOARD_SPECIFIC_LED
a84774f5	225	/* use LED0 to indicate booting/alive */
23fd959e	226	#define STATUS_LED_BOOT 0
a84774f5	227	#define STATUS_LED_BIT GPIO_PF2
23fd959e MF	228	#define STATUS_LED_STATE STATUS_LED_ON
23fd959e MF	229	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
a84774f5	230	/* use LED1 to indicate crash */
23fd959e	231	#define STATUS_LED_CRASH 1
a84774f5	232	#define STATUS_LED_BIT1 GPIO_PF3
23fd959e MF	233	#define STATUS_LED_STATE1 STATUS_LED_ON
23fd959e MF	234	#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
a84774f5	235	/* #define STATUS_LED_BIT2 GPIO_PF4 */
23fd959e MF	236	#endif
23fd959e MF	237
cf6f469e MF	238	/* define to enable splash screen support */
cf6f469e MF	239	/* #define CONFIG_VIDEO */
3f0606ad	240
3f0606ad AL	241
3f0606ad AL	242	/*
cf6f469e	243	* Pull in common ADI header for remaining command/environment setup
3f0606ad	244	*/
cf6f469e	245	#include <configs/bfin_adi_common.h>
9171fc81	246
3f0606ad	247	#endif